G13_DESIGN OF CMOS 45NM BASED FRACTIONAL - N PLL

[@HARSHAVARDHANPOTHULAPALLY]

I think loop filter is not there !

[@pratyushapvs9384]

Very nice explanation of the PLL circuit. My question is the output of the VCO should go back to the PFD as a feedback signal right? Please explain why are you using a different feedback signal for the simulation? Thanks!

[@landrover8135]

i guess it is coming from a clock divider

[@lp2045]

would really appreciate a clearer diagram

[@TSHERINGWANGCHUK-b6s]

can you make a full video how you have made a schematic digram of each blocks

[@rahultheytv5347]

fantastic video , thank you for sharing info

[@parulntrivedi]

fantastic video.....can you please explain step by step guide to simulate phase characteristics of PFD in cadence virtuoso?

[@ATMEYAElectrocrats]

will help out in next video

[@lokeshthota7847]

Excellent bro

[@sirpikachellam9618]

Super

[@mohammedamirshaikh4396]

what are the values given to Vpulse of PFD ?

[@nandinivenkata1237]

Can you provide the detailed block diagram of D flipflop

[@harikishapasam2081]

Hii can you show me the inside D Flipflop Circuit

[@landrover8135]

What is the output frequency?

[@nigiditapradhan8654]

Can you please show how to plot Icp vs vctrl

[@sanathgudasi5911]

Bro need some help ASAP

[@kranthimorthala8901]

Can send the material of it How can I contact with u

[@LionHPshorts]

Can u share diffrent block daigram Can I contact with u

[@ATMEYAElectrocrats]

Which different block diagram

[@LionHPshorts]

@@ATMEYAElectrocrats I want to design all block in cadence

[@LionHPshorts]

@@ATMEYAElectrocrats I am designing high frequency pll like 8-10Ghz

[@LionHPshorts]

@@ATMEYAElectrocrats please help

[@tony5r000]

@@LionHPshorts did you get the files, i want it too