Pipelining- Question 6

[@sathyaau]

Your lectures are extraordinary. Keep up the good work

[@sathyaau]

The operands fetched in the OF stage is used in the PO stage. So, for I3 PO stage can be in 11th clock cycle. Coz, it will be taking the output of ALU to give as input of ALU( You said in one of your previous lectures) The same goes for I4 also. So, the answer 13 is correct.

[@0pini0n21]

If x-axis is cc and y-axis is stages total ccs for all instructions are 13, Is this method correct ?

[@alagurajan4460]

design the following set of instructions using a 5 stage instruction pipeline. if any hazards occur, identify those hazards and redesign the pipeline for rectifying each hazard. find the number of clock cycles taken to complete the following sequence of instructions. assume all stages take one clock cycle each to complete the operation. a. add r2, r1, r0 # r2 ← r0 + r1 b. mul r4, r3, r2 #r4 ← r3 + r2 c. sub r6, r5, r4 #r6 ← r5 + r4.sir can you solve this problem and send the detailed answer?

[@mrinmoyhalder7293]

when , solving for gate qsn, we should assume split phase or not ??

[@ramasivasubrahmanyampedire8660]

By default you should consider ...unless they mentioned about split..

[@nimmibhangu]

sir if they asked this question in numerical answer type question where they don't mention any option then wht to do? please clear my doubt

[@rajdeep8195]

Sir 4th instruction not fetch in 4th clock cycle ,because already 3rd instruction store in buffer ..am I right?

[@chiragshilwant886]

Ya it should be 11 I think

[@SHASHANKRUSTAGII]

Best teacher

[@tuantran-cs]

Dear sir, Can we put IF of I4 at cycle 11th? Because I follow clip pipelining - Question 3. Thank you so much

[@uttukoul]

Same question.

[@ramasivasubrahmanyampedire8660]

Yes you can...

[@sanjeevkumarsen4838]

It is the numerical type question answer

[@nikitasinha8181]

Thank you sir

[@gokulsapra3371]

thank you so much