How To Improve Your PCB Layout - VIAs

Commenting on a PCB Layout done by a junior engineer.
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[@dvatp]

Even as a seasoned layout guy I can always learn from others' mistakes. More "before" vs. "after" type layout videos would be great.

[@RobertFeranec]

Thank you dvatp

[@aniketghosh8812]

For someone at an early stage of PCB designing, this kinda videos help a lot as you can learn and save time by not repeating the same common mistakes made during designing.

[@RobertFeranec]

Thank you Aniket

[@dmytrokorseko518]

Exactly, it is very important to pay attention to currents flows and their directions.

[@pnjunction5689]

This is great content! I like this kind of video format. Thumbs up!

[@RobertFeranec]

Thank you very much Pn

[@EDGARDOUX1701]

This is great Robert, would like to see more like this one. Your experience is very valuable to me/us. Thank you for sharing and time effort taken.

[@gudimetlakowshik3617]

Loved the video, after looking at some points of the video I realized how wrongly I've been designing boards all along. This is such an awesome content and I would love to see more of this. You're awesome..!!

[@Amirkheir]

thank you to make these type of videos and help junior engineers. thank you so much

[@yizumi7980]

I'm just starting with pcb layouts, im in the 2 layer board phase yet, but even do i've learned a lot from this video, thanks

[@adampunchki1148]

I really like this kind of format! Definitely great to have someone point out the small things that go unnoticed and say why they can be better. Regarding what you say at the end of the video, YES! I think we would all love to see more of this type of video :)

[@RobertFeranec]

Thank you very much Adam

[@douglasacramer76]

Definitely a nice style video. Good to hear you review the things you would change.

[@RobertFeranec]

Thank you very much Doug

[@dragandugandzic3970]

Thanks Robert, Great tips. Keep up the good work.

[@RobertFeranec]

Thank you very much Dragan

[@victorbosa95]

This kind of video is really useful. Please keep doing this kind of videos!! Thank you for your work and effort!

[@RobertFeranec]

Thank you very much Victor

[@SoorajGopakumar]

Thorough as always Robert :)

[@sergeymishuroff1254]

Robert, thank you so much! Your video and your description the most usefull on youtube

[@RobertFeranec]

Thank you very much Sergey

[@craigrmeyer]

This stuff is so awesome. Much appreciated.

[@Nida-e-haq]

I am a big fan of You sir. Lot of respect for your precious work

[@RobertFeranec]

Thank you

[@andreneves3597]

Great job Robert. Thank you

[@RobertFeranec]

Thank you very much Andre

[@hugopristauz3620]

excelent to learn from mistakes, excellent lesson! This kind of video is of incredible value. I made my personal notes and figured out 10 lessons. My 5-cent suggestion is to add segmentation marks to the videos related to the lessons and assign segmentation titles. E.g.: 00:00 intro 00:42 one via per ground/supply pin 03:35 consider current flow ...

[@haribabuk850]

great video ,do more videos like this sir . thumbs up!

[@m4l490n]

This is a very nice video, I really like this format, it's really more useful. Thanks for doing this. Instead of spreading the vias you can just remove the unused pads, that will help the copper flow in between them, that would save space.

[@mortezaghorbani7927]

awsome as always. your layout review series is really helpful and informative. please keep it up. thanks a lot

[@RobertFeranec]

Thank you morteza

[@giannisasp1208]

Very nice tips Robert! These kind of tips are always useful even for more experienced designers just as a reminder of best practice when designing pcbs.

[@RobertFeranec]

Thank you Giannis

[@tythagoras5787]

This is great, I don't know how your channel escaped my notice, but I'm subscribed now.

[@RobertFeranec]

Thank you very much Tythagoras

[@krisjk999]

Very useful. I had made the mistake of keeping all the vias together and making the cuts in planes. Really useful tip

[@RobertFeranec]

Thank you Jayakrishnan

[@ABaumstumpf]

Via in pad - in a small project with a friend we really used them a lot - tiny board, nearly no space (the size had a hard limit). Where ever we had larger pads and could we also placed vias in them to help with current and heat. We even used vias in pads together with throughhole resistors as there was no other way to connect the parts. Well - that just happens when you got 3 active chips (over 40 signal connections) and 3 inter-board connections on a 24x24mm board.

[@yaghiyahbrenner8902]

wow bless you these are brilliant tips many many thanks for putting in the time for this.

[@RobertFeranec]

Thank you very much Yaghiyah

[@p_peja]

For decoupling capacitors, sometimes I like to use 2 or 3 vias for GND and ONLY one for power. The idea behind is to create best possible connection to reference-GND plane while in the same time introducing a bit of impedance before connecting to power plane. That is how I can keep some of HF noise created from power pin of IC away from the power plane.

[@wrekced]

Thanks again! Looking forward to the next one...

[@RobertFeranec]

Thank you wrekced

[@guillep2k]

Yes, more of this please!

[@RobertFeranec]

Thank you guillep2k

[@user-zi1hf6xn2w]

Спасибо, Роберт. Хочу следующую часть.

[@ekirshin]

It's a nice video! Would be great to see the next parts.

[@RobertFeranec]

Thank you Evgeny

[@myetis1990]

Again a great job, thanks. Every time I wonder whether you have favorite Ic s for various connection interfaces such as USB host IC, HDMI controller IC, Ethernet IC, Audio IC, etc. can you share your favorites? And tell why are they your favorite. Sometimes people, especially juniors, stuck with the IC selection, so it would be a good start point for them.

[@gregfeneis609]

16:00 And, sometimes, the datasheet indicates that use of the central pad is optional. In that case, you can leave it out of the footprint and gain some advantage with routing

[@jeromes9306]

Great content!

[@huynhngocthienvuong541]

Great video!!!

[@nhuphan6969]

thank you for the video !

[@fase144]

Very good video, I really like it. Thanks for the informations!

[@RobertFeranec]

Thank you fase144

[@Helena-gp8bn]

Very clear, intresting and helpfull. I hope you will do more such reviews layout.

[@RobertFeranec]

Thank you Helen

[@paveld1409]

Good job! Respect to you!👍🤝

[@RobertFeranec]

Thank you Pavel

[@myhobbies5965]

Very informative

[@ismailovali6368]

Thank you so much Robert, I like you very much :)

[@MihalyBarasz]

Very instructive video, thank you! I would subscribe, but I'm already subscribed. :)

[@ANTALIFE]

Absolutely agree with your point at 18:00, VIA's should not be placed over pads unless there is an exceptional reason I recall at my old work we had an issue that arose from this. At one point we had to switch a PCB fab house for a board which we had been manufacturing. When we assembled the new batch of boards all failed in the same way. Luckily our technician was pretty familiar with the design and was able to pinpoint the fault to a broken track, which as you guessed was between a VIA and a pad. The VIA was just touching the pad, which was electrically correct as there should have been a connection between the two (even though there was no track between them). When the new PCB fab house saw this they flagged it as an error and broke the connection, without telling us ;^)

[@RobertFeranec]

Thank you Antalife for sharing your very interesting experience.

[@DarkoObretan]

Thank you Robert for doing these videos. I have small remark: Those pullups (at the beginning of video) are for I2C bus, and can have only one power supply via, I always do that, but for other 'real' power supply and grounds I agree and on critical power supply capacitors I put 4 vias per cap (and even that comes with sort of a limit, because if you put vias too close to another via with the same net, via inductance increases because of their coupled magnetic fields, so it is better to just put vcc and gnd vias as close together to have lowest possible via inductance)

[@RobertFeranec]

Thank you Darko

[@DarkoObretan]

@@RobertFeranec Now you got me thinking. It would be great to simulate what is really the effect of different via/cap/track placement for some standard 4L and 8L PCB stack (and also for wrong placement/routing, it might not be as bad as we think. I had to change my view many times so far and even some time ago I would not believe that too many low ESR caps can be worse than lack of decoupling capacitors!(Eric Bogatin PDN)). I always tend to have GND & power track from capacitor to the chip on top side, but that might be better only for 2 and 4 L PCB, for 12 layer it is probably not any more, because prepreg thichness is much smaller and total loop inductance is probably smaller with 2 additional vias when going to GND plane and back to chip. Someone could simulate that :)

[@RobertFeranec]

@@DarkoObretan I am currently working on a decoupling capacitor video (for couple of months now talking to 5 people from different companies - I am actually having a call with Eric Bogating later today) and I am very surprised ... it is completely changing my way of looking on power delivery. I am learning also simulate ... so once the decoupling youtube video is out, I can do more simulations on different topics so everyone can see what is actually happening on PCBs

[@DarkoObretan]

@@RobertFeranec Great news. I have so much respect for Eric Bogatin, Howard Johnson, Rick Hartley, Lee Ritchey, Doug Smith, Ralph Morrison, and some other signal integrity specialists. There is so much to learn and especially after reading all those books (after many older books with only one perspective) I see that there are too many rules or some of them are outdated, so someone really needs to set grounds and simulate/measure what is really important and what is not (and to which degree is not and when does it start to have an effect). Have a great time talking to one of the best, I'm almost jealous :)

[@gsuberland]

​@@DarkoObretan Big +1 on Rick Hartley. His talk on the importance of PCB layer stackups was one of the biggest learning experiences I've ever had in electronics.

[@mdchethan]

definitely liked it Robert, the layout review technique is not something someone can easily find in web I believe. Eager to see the next part.

[@RobertFeranec]

Thank you Chethan

[@zhitailiu3876]

Thanks Robert, nice video for all of us. For vias, consider them as inductors. Thinking that way we would place them carefully.

[@RobertFeranec]

Zhitai, thank you. PS: I will try to find more information about using more vias

[@przemo55555]

It would be great if you add more such layout review videos. Learning from others's mistakes and remembering some of our own that surely most of us once did :)

[@RobertFeranec]

When I see some interesting designs, I will make more layout review videos. Thank you for watching

[@claudiolorini3311]

This is gold!

[@RobertFeranec]

Thank you very much Claudio

[@oktemee]

Great video, Please keep on commeting on the board. Possibly best way to learn hardware design.

[@RobertFeranec]

Thank you Kerem

[@delereorbem]

I already give you like before seen the video, i know is good material.

[@RobertFeranec]

Thank you delereorbem

[@circuitdesign1520]

great video Robert Feranec, a question is it possible to round the edges of polygons using some rule?

[@eimc2707]

Thank you, I am still confused with Via, could you please explain what is the function of that?

[@yuanhu8174]

Great ！is there any chance to compare the sketche routing of PADS WITH ALTIUM/orCAD auto routing？

[@movax20h]

Good content.

[@RobertFeranec]

Thank you movax20h

[@mohamadchamrami]

awesome

[@SavageKing1292]

Nice video I use to do this when I was working 😔

[@devikadevika7259]

As fresher I am very much confused regarding placement layout what is layout planing what r the steps we should include while doing layout planning

[@le8a9p]

excellent video!!!, what is your approach regarding the grid, for example, try to put all components, tracks and vias in a given grid so that later routing can go through it, or would you rather just place them organically and let the tool push them as you route the tracks?

[@RobertFeranec]

Thank you LocoArdi. I do placement on a grid ... depends how small components I use, bigger component bigger grid (e.g. 1mm) smaller components smaller grid (0.1mm). Also, often i try to route at 0.1mm grid, but that is not always possible. (I do it, to make it easier for the tools and maybe get a better precision, but that is just my theory, I am not sure if it can help with precision)

[@ardaklc7617]

Thanks

[@hassanway6465]

How can i learn to make compatible schematic ? Please answer

[@Yankee14ed]

Hi Robert, great video as always. Around 19:00, you talked briefly about via-in-pad technology, and how some of the solder will get wicked into the via. I did watch your very in-depth video about via-in-pad technology, but I can't recall if you touched on whether ordering boards with HASL applied to the pads can help with this? For example, I just ordered some 4 layer boards from JLCPCB that used few LGA components where I was forced to use via-in-pad. I ordered the finishing with HASL, and noticed that the HASL process has basically pre-filled my vias with solder. Do you think this mitigates the effect of losing solder to a via, if the via is already full of solder to begin with? I recognize that HASL would probably not ever be used in a professional mass production assembly process.

[@RobertFeranec]

Thank you Yankee. PS: Good point. I have never really thought about this as we normally do not use HASL. I am just not sure what will happen with HASL when PCB is heated up, but you may be right, maybe it could help (?)

[@sirinsovalye]

if via is under ic, you should use tented. if you didnt it causes short circuit and pcb blows up :)

[@VasiliyVorobey]

Thanks for the nice video, Robert! At 8:10 you've said that you prefer to use the "pad-via-pad" style instead of "via-pad-pad". But it's the matter of your PCB stack, isn't it? The designer's ultimate goal is to achieve minimum inductance between IC and power rail. It isn't clear from the video, but I believe that 12-layer PCB must have a dedicated +VDD_1V8 plane at inner layers, right? And so, the "via-pad-pad" connection style would be preferable only if +VDD_1V8 is located "far" (more than 10 mils or so) from L1. If that PCB has +VDD_1V8/GND pair close enough to L1 (L2/L3 is most preferable ) - the best option would be to use the "pad-via-pad" style, isn't it? Wish to hear your opinion on that topic

[@sharana.p5921]

Hi, Mr. Robert Feranec. How to do via fill in altium?. Means filling vias with solder mask. Is there any option like that? Thank you

[@RobertFeranec]

Sharan, I would recommend to watch this video, it can be useful for you - we are talking there about a lot of things around VIA: kzbin.info/www/bejne/fH6WoYWDZairfdk

[@Andrew-dp5kf]

I started to pay more attention to putting vias off to the side of decoupling caps rather then off the ends as I saw in an app note how placement of vias affects capacitor inductance. Also where there are (physically) large capacitors for power I use a larger copper area placement on both ends do (not sure what you call them in altium) around and place many vias around it to help. A causal distrust of vias plating thickness helps keep the mind focused ;-) I always use gcpreview to double check the gerber plots to spot ground plane slots, good practice but annoying if you spot something!

[@dvatp]

I use two vias per side of the capacitors as well. I forget where I learned that technique but enough people don't do this that it should probably be the subject of another video.

[@RobertFeranec]

I also like to place vias on sides of capacitors ... just ... in many designs what we do, we are happy if there is any free space to place a via at least somewhere :( Great tips Andrew.

[@Andrew-dp5kf]

Robert Feranec here’s where I found that tip about the caps ntuemc.tw/upload/file/20120419205619a4fcf.pdf cherryclough.com/media/file/EMC%20for%20PCB/Part%205a.pdf Whilst I’m at it, these were useful for buck converters rohmfs.rohm.com/en/products/databook/applinote/ic/power/switching_regulator/converter_pcb_layout_appli-e.pdf www.richtek.com/Home/Design%20Support/~/media/DT_PDF/EMI_design_tips.pdf m.kzbin.info/www/bejne/naKQYY2mmKygbqc m.kzbin.info/www/bejne/anvIZHd4fptrfpI There are disappointing few app notes for boost converters :-(

[@RobertFeranec]

@@Andrew-dp5kf Awesome resources! Thank you very much sharing.

[@p_mouse8676]

Doesn't multiple ground pins on the same ground pins/area create micro ground loops? I am actually curious about via stitching. Some people really seem to overdo it.

[@RobertFeranec]

I am learning a lot these days a I hope I will be able to simulate all these things

[@anshaggarwal2060]

Hi Robert! Thanks for the wonderful Videos. I was interested in taking the course on Udemy but its with Altium and I don't have it. Does it make sense to still take it. I'm using Easy EDA FYI. Thanks in advance

[@RobertFeranec]

Thank you Ansh. I know, some people use different CAD software with that course e.g. KiCad instagram.com/p/BwZlCz5h0vO/? Maybe it could work also with Easy EDA?

[@YavuzAyrak]

Robert, it is very useful video for particularly junior and ones starting just to draw a pcb. I use sometimes region to connect power pins to the vias to reinforce the connection and reduce the heating that as long as it is possible. What do you think it is true to use region in this cases?

[@RobertFeranec]

Thank you Yavuz. Polygons will be done in this PCB almost at the end of the layout (especially for power and high current tracks)

[@jimjjewett]

@@RobertFeranec Are you two talking about, for example, 4:50? The design under review put tracks (and/or polygons) across the chip to combine 2 ground pins at a time, but didn't expand those tracks up/down to join the different pairs of grounds. Is there a reason not to do that (tombstoning? isolating the various ground pins from each other?) or would that be a good idea that you just choose to leave for the end?

[@krisjk999]

Any reason why the mounting holes are connected to the ground net?

[@RobertFeranec]

I usually do it, because if needed, you can always isolate the holes, but it would be difficult to connect them to ground if needed for some reasons.

[@averytijerina3425]

Also a general question for the community. I am new to Altium and the vias and tracks that I am reviewing are not filled with color, so it looks like a wireframe or a track that is only outlined and not a solid color track. Can any one help with this? Thanks

[@RobertFeranec]

When in PCB, press L -> View options -> Object visibility

[@JanJeronimus]

Hi Robert Feranec. After in the very past making PCB covering PCB copper board with nail polish and etching it with chemicals it is amazing how nowadays complex PCB can be easy and relative cheap custom manufactured. I don't make complex PCBs as in your video (my maximum until now is 2 layers) and learn a lot of your video's and explanation. I succesfully used one of the main PCB manufacturers.I expect it can become quite addictive. I have a relative simple question about VIAs that probably will be to simple in the context of your PCBs however it can be interesting for more people designing PCBs. I have seen a design where a track started at the top layer and continued on the bottom layer using VIAs. To make a better connection for thiger currents the top track continued a little after the VIA and two more VIAs from top to bottom track where added. Is this a right way to do (it create mini loops) or are there other (better?) options (e.g. bigger VIAs)?

[@RobertFeranec]

Thank you Jan PS: I do add multiple VIAs when higher current is expected to be carried through the tracks. And you are right, currents will flow differently through the VIAs however I have not seen any issues related to that (on the CPU boards what I normally design). If you like, have a look at this my video: kzbin.info/www/bejne/a2epp4SOa5h4l5I

[@jeanfernandeseng]

Robert, I am curious about Rule distances from via to pad, as 6:35 (yellow, ENET_RD0). When you runs the DSR, its raise some error (clearance via to pad ? ) Usually I put pcb to jlcpcb and I follow their capabilities and I d never put a via so close to the pad. What´s secret ?

[@RobertFeranec]

The rule you are referring to is probably the different net via-pad clearance rule. These are on the same net, so they can be close.

[@jeanfernandeseng]

@@RobertFeranec As suggestion, put a tip video regarding these conditions (same net, diff net) and comparing with capabilities of some manufacturer. Its important to new pcb designers. Thanks a lot.

[@GENcELL2014]

@21:35 it says hole to hole clearance is .54mm but bellow that it says via to via is .254mm(.01"). Looks like they allow vias to be closer than holes which I assume means a non PTH.

[@RobertFeranec]

I thought the same .. and then I spotted (Same nets)

[@GENcELL2014]

@@RobertFeranec Yeah noticed that too on further inspection. It does make a lot of sense, like two vias with annular rings of .005"-.006"(.127mm-.153mm) and a space of .01"(.254mm) in between equates to .02"-.022"(.508mm-.5588mm) via minimum spacing. PCBGOGO's standard manufacturing same net via minimum spacing is .2mm(.0078").

[@a1nelson]

Another great video. I didn’t really understand what you were recommending around 26:40. Placing vias first - that makes sense. But, how would one anticipate which vias to place in this region? Without the schematics and with only one layer being displayed, it’s hard to understand which nets are involved. Certainly, one would not want to randomly place the vias ;). I am guessing you’re referring only to ones connected to these particular differential pairs? But, it’s a little unclear how to anticipate what vias will be required - before drafting some of the tracks in. Could you maybe elaborate on this in the comments or in a little follow up video? No obligation, but I would appreciate it, if you have the time. (I did work through your Altium course, so maybe I’ll review the schematics and that will help answer some of my questions. However, I have the feeling that other people may have the same sort of questions regarding this area.) Regardless, thanks again for your contributions to the community.

[@RobertFeranec]

Thank you a1nelson. There are components on the top and on the bottom layer (visible in the video - grey color). Almost all the pins on these components will need VIAs (except the pins which are connected to the components placed close to them). So, almost all the power and ground pins for chips and decoupling capacitors and all the signals which you will have to route inside of the PCB will need a VIA (including the signals what are connected further from the chip or for example buses and interfaces).

[@a1nelson]

Oh, I see it now. I had to go back and forth in the video to grok it. In the zoomed-in view, around 26:40, it was the ratsnest lines that were throwing me off. Rather than being terminated at two points, they gave the illusion that some of the transmission lines also had a third termination, as might be used for TVS on Ethernet or USB. After reviewing the video, I see that this illusion simply results from the routing of these lines being incomplete (and a bit wonky). You mentioned that this was a work in progress, but for some reason, my eyes just didn’t pick up on the gaps in this area. Thanks for the explanation!

[@RobertFeranec]

@@a1nelson it was just a draft to get an idea if it will be actually physically possible to fit the tracks there and how much space we still have.

[@hugopristauz3620]

Danke!

[@RobertFeranec]

Thank you very much Hugo

[@sreedharan6377]

Thank you so much sir, i need to know the components placements tips also, anyone suggest me please...

[@RobertFeranec]

Component placement may be very specific for the circuit you are designing. But maybe this can help: kzbin.info/www/bejne/np6nZXiqeqtlqbM

[@huytung3144]

can you help me creat translation of video ? thank you so much

[@abdalahbesho1916]

hello robert , i'am great you for that effort ,but i'm beginner in this program and take altium20 version for six month ,and you make tutorial for begineer but for altium19 and i found many different in place of order , so can you give me an advice or videos from your channel to help me understand well

[@RobertFeranec]

It is difficult to keep up with Altium changes. However you should be fine - versions from AD18 are similar. PS: If you have any specific questions, you can ask on our forum here: designhelp.fedevel.com/

[@MaximYudayev]

What about increased EMI because of increased number of current loops as the result of this? What is your opinion?

[@RobertFeranec]

I have never had any problems with that. However I am learning how to run proper simulations and hopefully once I will be able to simulate also these :) ... and make videos about it of course

[@MaximYudayev]

@@RobertFeranec Thank you for great content!

[@DarkoObretan]

If I would have to guess, I would say it cant be worse, because total EMI is product of dI/dt and those two stay mostly the same if you look from perspective of power pin. Actually there will be some increase of peak current because of better (lower inductance) decoupling, but it will emit from ever so slightly different places and therefore be out of phase at certain frequencies so some of it might cancel out. And current loops will be with lower inductance (pwr tightly coupled together), so therefore I expect less radiated EMI. We will see what really happens in future video.

[@averytijerina3425]

What component was FB2?

[@RobertFeranec]

It is a ferrite bead

[@bobby9568]

@Robert Feranec Don't your hands hurt after long hours of pcb design?

[@RobertFeranec]

Some time ago I made a video about it. Also comments can help there: kzbin.info/www/bejne/e4iapXtrgsxkgrM

[@bahadrguven6268]

Would you please open the subtitle?

[@Andrew-dp5kf]

26:20 that explains the wonky looking vias I kept noticing, trying to avoid the diff pairs. The best tip I saw was to start placement with power (specifically buck converters) and high frequency components first, anticipating where the signals will need to be routed and the high current flows, then move on to other parts. It’s difficult, but as you say, saves a rip up and restart later.

[@RobertFeranec]

Reading between lines :) Well done!

[@wolfganglienbacher]

Amazing information as always! I'd still like to once more comment that I find the pace at which you are talking very hard to follow. I always watch your videos at 2 times the playback speed and it is much easier for me to follow. If you can, please, I'd really appreciate if you could talk faster. 🙏

[@RobertFeranec]

Thank you Wolfgang. As I am not English native, if I speak faster my English would be even worse and hard to understand. So I need to speak slowly :(

[@wolfganglienbacher]

Hey @@RobertFeranec, not a native speaker either, your english is perfectly fine!! 😉 Also the speed at which you pronounce words is fine, just pace at which you connect words is veery slow. Also keep in mind, when something is too fast for somebody, you can always skip back and listen to this segment again. This was a particularly interesting video by the way! I'm frequently sitting in front of my designs wondering about exactly the questions you answered 🤗

[@foobarables]

The vias you are talking about at the start of the video seem to be connected to pull-up or pull-down resistors. No big deal if its only one resistor. However, the problem here is the placement of those vias. How much solder mask is left between the resistor PAD and the via hole? Around 6:30 you speak about high speed problems around those vias. Here I also don't see the problem because they connect pull-up resistors and trance inductance is not important any more. The real problem here is optical inspection problems caused by the traces between the resistors if there is no solder mask between those resistors. You also have to look at the solder mask if you see something like this. (and think about the solder mask manufacturability). At 7:10 you have acid traps (pin66 and pin 67). The same construction can be seen in other places of the board. What you did with the via at 8:20 is also not preferred because of uneven heat distribution during soldering. In those places, via placement is a trade off. A lot of vias connecting decoupling caps to planes are being placed into the SMD pad edges. You do not completely explain how close a via can be placed to an SMD pad. This might be interesting for the person who designed this board and some of the people viewing your videos. You might want to investigate how ferrite beads behave. They don't do what you think they do and very often cause unwanted resonances. Low value resistors are a much better solution in many places instead of ferrite beads which people seem to sprinkle around everywhere because someone said so. Via count in plane decoupling caps is defined not by current only. The inductance of a via must be taken into account if you want properly decouple up to 300MHz. I use 1.6nH as a rule unless I need something better. An interesting video for many newbies might be a thorough explanation about design rules to follow and why. Also, you recently released a video on PCB tools and which one to select. For me it doesn't matter which tool you give me. After a few days you find out which button does what. I started with decals as a teenager...What I really had to learn was to properly analyse my board layout. Decoupling caps (and not just the "place them as close as possible rule"): how many and which type. How does trace inductance affect my signals and PDN on a two layer board. How many via's do I really need in my high power SMPS and in which places via's should be avoided at all cost? Stray capacitance, cross talk,... How do I really connect an xtal to a microcontroller (guard traces and current flowing under your xtal oscillator traces)? Do I need termination resistors on my SPI signals? Just to name a few. Those are the things you need to design a robust PCB and to pass CE without unnecessary components. Basic circuit analysis is all you need. Most people new to circuit design and board layout seem to struggle with this questions or they just do something which they think is good enough. What do I really measure on my board with and oscilloscope? Is it good enough and how can it be improved if required?

[@filipp3327]

Nightmare for Junior Hardware Engineer. Shall we discuss about PCB or Layout check list?

[@km5405]

there is no subsitute from learning this stuff from a experienced engineer.

[@RobertFeranec]

Thank you very much Kevin

[@DashCamSerbia]

8:30 I don't realy understand the problem here.

[@SavageKing1292]

I am a pcb designer in for 6 year now I lost job in this pendamic please any one help me for a job 😭

[@azretbotash4743]

Thank you...

[@Usturam]

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[@OpenFrimeTVcom]

Please add subtitles!