Implementing a combinational logic circuit in VHDL using Quartus Prime Lite

[@gregben]

Thanks for creating this tutorial. The logic you create with VHDL and place in the FPGA is not "simulated". It is real logic. I should know, I've been working with digital logic since 1975.

[@Sonic2ist]

very helpful step by step tutorial. thank you very much.

[@farnazzinnah8541]

It's worth to subscribe to his channel. He helped me finishing my project in one go. Thank you!!!!

[@warleyxavier7142]

Thanks for your tutorial!

[@namugwanyamarypatience7039]

Thanks for the very helpful video. What can one do, incase the simulation runs for longer than the set time? What could be the cause of that? I have followed your steps but my simulation runs for more than 10 ns.

[@김서진-n3y]

Thanks for the tutorial:)

[@mayankpatel7973]

I followed the same step as u but my compilation and analysis both are unsuccessful , in analysis it is stating that top level design entity is undefined kindly plz guide me as I have to submit some codes and simulation

[@adivhahoradziuhuni9059]

did you figure it out?

[@PengJin-i8k]

thank for ur help

[@idasol2966]

HI It is very good. The best one, but You did not show us how to write the code, You just copied it. Thanks