#1195

[@SeanBZA]

They can also oscillate during this drift, just from the capacitance between pins and traces, making the other half of the gate misbehave. 10MHz plus for the HCT series, around 2MHz for the cmos, while the ttl stuff totally is fine.

[@briansauk6837]

Good trick for low current measurement is to take any multimeter (even a cheapie handheld) and use the volt scale and connect as if set to current. Essentially that is giving you a 10M shunt. So a reading of 10 mV will be 1 nA.

[@NavinF]

It’s a good trick, but the burden voltage is way too high to run chips through a meter’s input impedance.

[@briansauk6837]

@@NavinF the trick works just fine for low current chips like cmos where it is nA or less. The burden voltage is simply the displayed voltage - if you are seeing a few mV there is no problem at all.

[@nickbolton9435]

Extremely helpful video on why to tie inputs low/high. I usually do this to avoid weird behaviour but had no idea about the current draw. Great video!

[@HeyBirt]

The TRS-80 Model 100 SRAM backup battery also keep a few of the CMOS logic chips powered that are part of the reset circuit. This is so the machine will power up and reset properly and not trash the RAM. As you have demonstrated the chips draw so little power in a steady state it is not an issue for the 80mah battery.

[@JenkinsUSA]

Thanks for pointing out the CMOS floating tip! 🎈

[@argcargv]

Technically speaking tho output of cmos gates is push pull. Totem pole would be what you would use without the complementary output transistors, e.g. two npn or two nmos transistors. Totem poles can't source and sink the same amount where a push pull can both be good sources and sinks.

[@absurdengineering]

Totem pole can do it all… with a little charge pump to help out :) The pump output only drives the gate or base, so not much capacity needed.

[@Enigma758]

Good practical lesson! Just for fun, it would be interesting to see if the current draw was any different if the unused inputs were instead tied low.

[@RexxSchneider]

It would be astonishing if the current draw were any different. Unlike TTL, the inputs of CMOS logic draw no current, so there would no difference in current through the inputs, whether high or low. Since the output stage is push-pull, when it is high or low, one or the other mosfets is turned fully off and so there's no current path between the rails no matter whether the output ends up high or low.

[@willthecat3861]

There are high-side switche ICs, in surface mount, switching the low single digits of amps: for example, with maybe lower on resistance than a discrete P channel FET: for example 30 mOhm on resistance, for a high-side switch. These ICs are speced to have about the same quiescent current as the 74HC74... that's a couple of uA. There is also at least one high side switch (a pair of them) in a DIP: but, it's expensive, and has a higher quiescent current than the SMT parts.

[@jainmanish123]

Nice explanation, because of the low standby current of cmos devices even a small dc bulk cap can hold the state for days. The main supply and memory supply (dedicated bulk cap) separated by a diode. We used to use this technique to hold count, state in timers and counters without the use of any battery and external power. Good and important demonstration of the standby current with floating and tiedoff inputs which is the key to above. Thanks

[@t1d100]

I noticed that you DIY'd a pair of breadboard switches from SMD tact switches = good substitute. However, I thought folks might like to know that the common, black, four-pin, PCB-style tact switches also come in a breadboard friendly, long pin, two-pin model. They are available from the cheaper sources, like Ebay/Amazon, but you do have to look harder to find them. They are very handy and, therefore, worth the effort to search for them.

[@8-bitbitsa821]

The increased current draw seen when inputs are left floating is mostly due to oscillation. If you scope the outputs associated with those inputs, you’ll see them oscillating, sometimes up into the tens of MHz. So it’s not just the floating inputs “floating” to mid-rail and turning both output transistors on together causing the higher current condition, they’re causing the gate to oscillate with only the smallest trigger signal (noise) at the input 👍🏻

[@boonedockjourneyman7979]

In 35 years of fooling around with TTL/CMOS, I don’t remember ever actually testing this. Unbelievable change in the world. We didn’t even check power consumption.

[@absurdengineering]

Just so there are no surprises for the young players: the idle current would get a bit different if a heat gun was pointed at the chip for a few seconds. The channels of the devices that are turned off will conduct quite a bit more as they get hot :)

[@johnwest7993]

Random self-oscillation charging and discharging the gates of the totem-pole FETs of the unused flip-flop due to floating inputs. It happened to me when I first used CMOS. And worse still it created noise in the output of the flip-flop I was using, that made my circuit erratic because both flip-flops on the chip are built on the same substrate. So floating inputs are the first thing I look for with erratic CMOS circuits.kzbin.info/www/bejne/oZKloZWpqs2og6c

[@zyeborm]

The three states of digital logic, on, off and #$&#ed as my lecturer once described it lol

[@t1d100]

Thank you. Good info.

[@MikeFikes]

I'm now wondering if a Joulescope can give some insight into the rapid current draw fluctuations when the unused CMOS inputs are left floating.

[@tubeDude48]

1 of my favorite chip. Along with 74HC195

[@gerd3136]

Good to know, thanks a lot :)

[@davidharms3562]

Great video! Thanks for the great content!

[@DonzLockz]

Seems simple when you explain it. :)

[@AnalogDude_]

good video, good job.

[@iblesbosuok]

I prefer 4013B. Fit for slow network.

[@willthecat3861]

74HC74 has 32 gates? (so 128 FETs?) ... the lowest worst case quiescent current I could find (quiescent current varies with temperature) ... the lowest quiescent current I could find for a 74HC74, on a data sheet, was in the order of 1 uA. In the video the measured value of 1nA is three orders of magnitude better.

[@RexxSchneider]

The datasheet I have for the 74HC74 only gives maximum values for quiescent current, of 40μA at up to 85°C and 80μA at up to 125°C. CMOS is quite sensitive to temperature when it comes to leakage, so I wouldn't be at all surprised if a typical quiescent current at room temperature was no more than a few nanoamps.

[@willthecat3861]

​@@RexxSchneider The worst case at room temp. quiescent current I can find is in the low uA range. A measured value of 1000 times better seems too better? The manufacturers may have a reason: maybe to be able to sell as many parts as possible, given there is such a wide? manufacturing tolerance. It'd surprise my boss if I designed for worst case of 100 nA (still two orders of mag. greater than measured.) and only one in 1000 parts met that spec. (Probably, I'd be more surprised than my boss at the result of designing like that.)

[@RexxSchneider]

@@willthecat3861 The Onsemi datasheet I just found dates from 2007 and indicates a guaranteed maximum of 2μA at 25°C, 20μA at 85°C and 80μA at 125°C. The datasheet I quoted before is from Nexperia, dated September 2021. Specs do change over time. Now, the thing about a _guaranteed_ maximum is that it is inevitably much larger than the typical values, because a manufacturer has to cater for parameters varying many standard deviations from the mean to ensure that actual parts will almost never exceed their guaranteed limit. The static supply current for CMOS is effectively leakage current only and that can vary quite a bit in production even for room temperature measurements. I still wouldn't consider a typical leakage current of the order of nanoamps unlikely at all. Even if the manufacturers have to quote a figure 1,000 times higher than typical to be able to give guarantees, I don't see that as unlikely. When you're designing for a particular application, you have the ability to make decisions about the level of risk you're prepared to take. If you're designing battery-powered equipment located in unserviceable places, your boss is going to thank you for designing for a worst-case drain of 2μA at room temperature. Because even if the battery life turns out to be typically 100 or 1,000 times what you've designed for, that is a far better outcome than designing for 100nA drain and then finding later that you had the one-in-a-million poor part that was drawing 1μA and the battery dies well before its expected service life. Obviously, if changing or charging a battery isn't a problem, you can cheerfully take a higher risk and design for currents much nearer the typical values that you can measure when prototyping.

[@willthecat3861]

@@RexxSchneider Hi, yes I agree on all points. But, I never encountered any suits working for a manufacturer of anything that wouldn't take advantage of a 1000 times better spec. to ... well, take advantage. That is to sell premium parts (1000 X better is premium.) Binning parts was a very commonDo you have the same measurements (or does anyone have) the same/similar measurements) across several production runs/manufacturers, of this part.

[@RexxSchneider]

@@willthecat3861 I understand where you're coming from. One half of the issue is that you can only sell premium parts if there's a market for premium parts. The other half is 74HC74s cost around 10p in quantity. The cost of testing and binning on such an unusual parameter as supply current would significantly increase that cost, and I'm not sure a market would exist for a simple logic chip that was guaranteed 20nA maximum supply, but cost twice that of the same part that was guaranteed 2,000nA maximum supply. How many projects would actually see any benefit? I've got a few 74HC74s lying around somewhere, but I've no recollection of ever bothering to measure their quiescent supply current, as I've always considered it was essentially zero. I guess I could dig them out and check. I've been retired for over 10 years now, so I've lost all my old contacts who might have been able to have given an up-to-date opinion.

[@lelandclayton5462]

Quick yet informative 1ST!

[@frankowalker4662]

Neat.