Interconnect Modeling (Part 1)

[@vamseemohanmallela6105]

Generally pitch is from the middle of the wire to the middle of the adjacent wire, but we get the idea. Thank You!

[@filipebemba2410]

ℹ o

[@chaturbhujrajendran4995]

The schematic of the inverter here is wrong. The source of Pmos has to be connected to Vdd. So, the drain of the Pmos and the drain of the Nmos are shorted together from where the output is taken.

[@choinimanikanta5357]

That schematic is correct Rajendran

[@vayalpadunirupa1697]

Why we won't consider inductor in net delay

[@telugujoshi]

It is a second (or even third) order effect. Sometime in the near future, inductors - self and mutual - need to be taken into account.

[@kranthikumar9998]

Sir, How we will get these ppt's?

[@anandmaurya4045]

www.ifte.de/books/eda/ Download all slides and reference book from here.

[@debarunsaha8485]

Sir,Drain of pmos and drain of nmos should be connected at the output.

[@nitinsonker8429]

yes there is some mistake on that rather things are ok