Internal Linear Feedback Shift Registers

[@Strebezhev]

Sir, I've been waiting for a new video from you for a whole month! Thanks a lot for such great content! I have a topic that I would like to clarify for myself. Could you help me understand how UART works in terms of FSM? Could you please explain step by step (as you usually do) which processes (I mean VHDL processes) I need to create and why? How should I understand from the testbench that everything is working correctly? Thank you very much for your hard work!

[@Intermation]

Thank you for the kind words! As for the topic suggestion, it's a great one. I was on a team with Dr. Armstrong out of Virginia Tech to work on the test suite for VHDL, but it's been years since I've used it. Maybe I should put together some VHDL lessons before tackling an implementation lesson.

[@Strebezhev]

@@Intermation Thanks a lot for the quick response. I actually have a PDF file that has UART codes for components using FIFO and a circular buffer. (Components RX and TX, sample application and "creating a file for workflow" and test benches for each part, which can be useful as a reference for creating a new video). The fact is that these codes do not have enough descriptions (in terms of FSM) to be understandable to a beginner. You will understand my question better if you see the implementation I have. Can I somehow send you this pdf file or a link to it?

[@gvenagas]

David Tarnoff you are a gifted professor and I thank God for putting you in my path. You have the ability to always be one step ahead of any question that may arise in the student, I feel like you read our minds. May you and your family always be healthy!