Introduction

[@jumblebee6018]

Revise your lecture here! | 0:55 Main objectives of the course 3:06 VLSI design process 8:19 Moore's law 11:28 Technologies (CMOS, FinFet and Quantum) 13:15 VLSI design flow 14:22 Need to use CAD tools 17:15 Two competing HDLs (VHDL and Verilog) 18:20 Simplistic view of design flow Steps in the design flow 19:37 >> Behavioral design 20:52 >> Data path design 22:43 >> Logic design 24:24 >> Physical design and manufacturing 25:50 Other steps in the design flow END OF LECTURE ONE

[@arafay142000]

Verilog HDL Complete Series | Lecture 3 - Part 1 | Data Types in Verilog HDL by FPGA made Easy. Subscribe to the channel "FPGA made Easy".

[@mbcreations4158]

Thank you

[@mohithasaiburi6824]

U're amazing...thank you ❤​@@mbcreations4158

[@ericmaclean6254]

This guy is literally the goat. If your seeing this and you want to learn verilog you have to watch this whole series.

[@Deepak_3860]

*To download pdf notes* *1* Type hardware modelling using verilog indranil sengupta notes . *2* go to assignments (see at bottom) & download it as zip.

[@rashikabobade4769]

@Deepak_3860 where to type

[@durgeshydv3829]

from where we have type for download the notes

[@AchuthaAswinNaick]

@@durgeshydv3829 google

[@iiitk_nani]

@@durgeshydv3829 google

[@soul2197]

Made for Indian sadly not used by Indians ,but mostly used by non Indians

[@xrayonthemove]

there are many vlsi engineers in india isnt it?

[@amanagarwal3497]

@@xrayonthemove only verification engineers, design engineers are very rare

[@vilasventure]

yes from SriLanka

[@mayanksinghal7904]

Very informative ! Thank you sir .

[@sriharshaml1173]

Any reference book for this course?

[@lavanyas8870]

Sir, can you please share the ppt that you used to teach us. It will be really helpful if you share sir

[@harir3116]

i have the ppt

[@saishanmukhchinimilli3264]

@@harir3116 wher can i find the PPT

[@harir3116]

@@saishanmukhchinimilli3264 im currently doing that nptel course.So the enrolled students can asses those slides.may be i can mail it to u

[@saishanmukhchinimilli3264]

@@harir3116 thank you but I found it on the website

[@illuruvigneswarreddy9469]

@@saishanmukhchinimilli3264 where did you find the slides..can u please send me the link

[@narayananr7065]

Can u pls clarify the synthesisable

[@kumarv4184]

Very good explanation sir

[@vaishnavikollurkar7556]

Sir can you explain me the Verilog code on APB protocol

[@nishatanwar2658]

Very nice lecture

[@randomyt5358]

Best sleeping Medicine ever

[@margoluca8328]

Sir,Can you share the PPT?

[@gopalakrishnab358]

🤣

[@TechYatri06]

So much helpfull

[@akhileshkumar-pt3dp]

anyone have notes

[@yasmeen2173]

hello have you an email can l contact with you ? because I have a project and I need to help to do my project please.

[@arafay142000]

Verilog HDL Complete Series | Lecture 3 - Part 1 | Data Types in Verilog HDL by FPGA made Easy. Subscribe to the channel "FPGA made Easy".

[@lavanyas8870]

Sir, can you please share the ppt that you used to teach us. It will be really helpful if you share sir

[@arafay142000]

Verilog HDL Complete Series | Lecture 3 - Part 1 | Data Types in Verilog HDL by FPGA made Easy. Subscribe to the channel "FPGA made Easy".