Inverter - 1 - CMOS Inverter Construction

[@jayparekh9768]

The way he explained that NMOS should be used in PDN and PMOS should be used in PUN was commendable.

[@sayanbaidya9724]

Anyone struggling to find the VDD/2 concept can refer the Inverter 12 - Nmos Transistor ON resistance and Inverter 13 - Elmore delay lectures

[@socialogic9777]

When did we come across the concept - discharge from Vdd to Vdd/2 for delay purposes? Also, in which lecture equivalent RC model was discussed?

[@ParminderKaur-zm4kw]

Yea, sir please always upload all the content.

[@adeddy8138]

Yeah i agree I am totally confused in here ? Partially understanding everything

[@socialogic9777]

@@adeddy8138 kzbin.info/www/bejne/oGrOfp1mjtdplbs This is the missing lecture, the first 27 minutes

[@adeddy8138]

I think some transistor capacitance videos are missing i am not understanding the vdd/2 concept ,and equivalent rc model and when did module 3 came from jumping from module1

[@heyitsmea8883]

When pmos discharging why vgs=-vc(t) didn’t get plz explain

[@adeddy8138]

I am totally confused in here ? Partially understanding everything when the concept of vdd/2 for delay purposes taught and when was equivalent rc model taught i did not came accross something like that plzzz upload the videos if anything is missed

[@ramankumar-re8xh]

have u got this videos or not ?

[@socialogic9777]

Why do we think in terms of NAND-NOR logic in CMOS?

[@VLSI260]

Because they are good at switching time and power consumptions and their logic efforts are less

[@gayatri5397]

Sir why is Vdd negative for PMOS charging?

[@akashekhar]

Revisit device physics. In pmos, channel is formed when gate voltage is lower than threshold voltage.

[@VLSI260]

Yes

[@silverfox7011]

@@akashekhar and why it is not vgs(t)=vdd-vc(t)

[@ajiths1689]

i did not understand the expression for charging ..please someone could you explain...

[@ajiths1689]

understand hopefully

[@anonymousinfinido2540]

​@@ajiths1689did you understand?