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FPGA #23 - Switch Debouncing

  Рет қаралды 851

John's Basement

John's Basement

Күн бұрын

Пікірлер: 9
@AlexOlsenpang
@AlexOlsenpang 2 ай бұрын
Wow, I never thought youtube channels like yours existed! This is great! I have always fixed this in software but this is also cool!
@JohnsBasement
@JohnsBasement 2 ай бұрын
Thanks for stopping by! Just trying to have fun sharing some hobbies.
@cristianstoica4544
@cristianstoica4544 2 ай бұрын
That design with shift regiater is he best I've seen for debouncing. I've seen it implemented in a chip in hw. Ive shamelessly copied their datasheet algorithm in sw and worked perfectly . The best algorithm in Jack Gansle page is similar but has some flaws that are not present with the shift register chip.
@cristianstoica4544
@cristianstoica4544 2 ай бұрын
For ref ONSEMI MC14490 is the chip
@MrBtcruiser
@MrBtcruiser 2 ай бұрын
I've been programming Cypress/Infineon PSoC devices which have universal digital blocks in them. You can use their design tool to drag functions (debouncers, glitch filters, PWM controllers, etc.) into the design which configures these UDBs and creates APIs in the source code to interface with the UDB function. They are light on describing what is really going on internally with the functions, and this has been helpful for me to gain a little more understanding.
@keastie6671
@keastie6671 2 ай бұрын
Do you think you could do a video talking about common data protocols used inside FPGAs like AXI4-stream? Love your work!
@JohnsBasement
@JohnsBasement 2 ай бұрын
That might be a bit of a leap from where I am at the moment. But it is a good idea. I will add it to my "some day" list.
@J.D-g8.1
@J.D-g8.1 2 ай бұрын
What is meant by synchronizer in this context? Why would the button input go to a synchronizer before going to the microcontroller?
@JohnsBasement
@JohnsBasement 2 ай бұрын
@@J.D-g8.1 It is a clock domain synchronizer. It is discussed in the previous video in the same playlist.
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