FPGA #14 - Verilog Always Pt. III (Synthesizable Design Patterns)

Standard Synthesizable Verilog design patterns for latches and flip-flops.
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#verilog

[@k3dr1]

Thank you for all the wonderful videos you keep posting, they are a great learning resource!

[@JohnsBasement]

Thank you for saying! It is nice to know I can help.

[@DavidLatham-productiondave]

Thanks for this. Theres a lot to unpack. I suspect ill be rewatching this one again before too long. I am always getting tripped up when a wire is needed vs a reg. Im excited about whats next.

[@JohnsBasement]

Reg if it is on the left-hand-side of an assignment in an always block. Else wire.

[@tconiam]

To properly emulate asynchronous set/reset you would have to have three separate "always" blocks. One each for clock, set, and reset. Otherwise you have the "priority" issue you discussed. (First match wins)

[@JohnsBasement]

With three, how would it be synthesizable?

[@tconiam]

@JohnsBasement I don't know yet, I'm still learning this stuff. Thanks for the education so far!!!