Learn Verilog By Examples - Single Clock FIFO

This episode describes why single clock FIFO is needed in FPGA/ASIC designs and then how one can write one such block. It also shows tools of trade using icarus verilog and gtkwave that are freely available on the web.
Code
bitbucket.org/...
Free Tools
iverilog.icarus...
gtkwave.sourcef...

[@ganauvm270]

can you upload dual clock fifo

[@TheMindGrid]

Please checkout dual clock FIFO in my plylist.