Lect43 Digital Design Flow using Cadence tools (By Saurabh Dhiman, PhD Scholar, IIT Mandi)

[@saurabhtrivedi6181]

Nicely Explained, and a very important topic for interview cracking as well

[@rishabhkumarsoni1240]

amazing content

[@DD27_27]

Very informative and useful. Thank you sir.

[@sanjeevsai9939]

Thank you very much sir, it helped me a lot for my B.Tech final year project

[@vivek3855]

Very nice explanation.

[@diwakarvoriganti3024]

Superb sir

[@shuvambiswas458]

Sir from where did you download the library file

[@PrashantSharma-tu9sp]

what changes you made in sdc in "create_clock" command ?

[@Ankitkumar-yg1wn]

Please make one video on system verilog or uvm using cadence.

[@RishiTiwari-dl9kk]

Sir, what is the clock frequency of your design.

[@RishiTiwari-dl9kk]

Sir, what is the clock frequency of your design?

[@AmirKhan_KnowTech]

I want to synthesize a decoder which has no clock. How come I can do it?

[@parulex2]

Hi Dr.Hitesh, Good explanation. The content is very much informative. But could you explain on how to download the library files and the conversion of the .src file to .v file. I wanted to do the same with TSMC 65nm technology for doing post synthesis simulation, could you please help on that too. Thank you.

[@14-ds-nagamanicholleti60]

Superb explanation sir. Actually I'm having RTL code, Can you please help me in doing synthesis for this to find area value sir.

[@vijay5193]

Sir, thank you for the video...but I need help in locating the relevant .lef and .io files for importing design in innovus...please tell me where...

[@usmankiani1017]

Could you please explain how the VCC and Gnd io pads are connected to the core ring

[@mohammadfazel1522]

Nicely Explaned! But I need files and libraries😢how can I download them?

[@easywayoflearning3014]

As soon as I give save and give ok the entire innovus is getting closed. And in terminal it's showing impvl

[@BangarGauravLaxminarayan]

where is cts ?