Lecture - 29 Memory Hierarchy : Cache Organization

[@vedhasp]

Good lecture all in all, Thanks IITs and IISc!!!

[@LigGLe]

@vedhasp I think what he means is, that with higher associativity you can avoid more conflicts. It's what he also said earlier. For example to reduce conflicts you could also use an 8-way associative cache. Or even fully associative. But with increasing associativity you also have an increasing complexity of the cache management. So, reducing conflicts results in higher associativity, but results in higher complexity. I hope it's the answer to your question

[@sachingangualy]

marvellous way of explaing ths tough topic thank u sir

[@joerokcz]

cache coherence is a type of problem which may arise in the time of access memory.when main memory is searching for a data from cache then it may happen that DMA(direct access memory) is also making a operation in that particular address of cache.then conflict may arise.this is called cache coherence,to get rid off off this problem,flushing is done about to the cache(only when this problem is occurred),

[@vedhasp]

How are we likely to reduce miss rate with 4 way set associative cache? He said "Reason being that if degree of associativity is low, there are more conflicts. And therefore, some of the blocks which you may like to use later on may get thrown out"

[@vedhasp]

@vedhasp This is around 16:05 FYI. Please help me understand this statement.

[@vedhasp]

@LigGLe Thanks for taking pains to write reply, I appreciate! My question however remains unanswered (sorry), awesome if you could try answering. "How/Why" would miss-rate get reduced with associativity increase?

[@vedhasp]

38:15 How often do you prefetch: "Again, its a tradeoff" Between???

[@Arpitgupta363]

wht is cache coherence?is this topic present in dis lecture?

[@MajikaUKBand]

How about less time on animated intro, more focus on sound quality!?