Lines

How to translate an algorithm into synthesizable RTL (System Verilog). Specifically, Bresenham's Line Algorithm implemented on an FPGA.

[@shivaramkrishnaaj9496]

Thank you so much.. Excellent video... please keep doing videos like this.. very informative... Unknown knowledge to billions...please please please keep doing ...🙏🙏🙏

[@user-ok8yj8ln3u]

Thank you! Great work! What software have been used to create timing diagram @9:23?

[@stephen70edwards]

I do all of those in LaTeX using a tikz package (timing?)