LMARV-1 reboot part 12: The sequencer

Working on the schematic for the sequencer.
nMigen exercises: github.com/RobertBaruch/nmige...
github repo for code: github.com/RobertBaruch/riscv...
RISC-V specs: riscv.org/technical/specifica...
nMigen tutorial: github.com/RobertBaruch/nmige...

[@ospis12]

over one hour, i'm here for a treat

[@hxt21]

yes, then it will be a super good weekend. Sides with a cup of coffee and will enjoy seeing the whole thing and enjoy hearing Robert tell. Best time.

[@obiwanjacobi]

Nice! Thanks for the video. And I'm happy to see I am not the only one to use hierarchical sheets as block/module diagram ;-)

[@havresylt]

1.5h of nerd heaven. Nice!

[@wChris_]

I want to see the Hierarchy of this schematic.

[@gsuberland]

I ran into the same net naming limitation in Altium recently, when trying to build a normally closed jumper footprint. Weirdly, the documentation specifically mentioned being able to build these NC footprints as jumper parts, but you can't do it without DRC errors and massive confusion about net naming. Instead you have to mark it as a net tie. Apparently the hierarchical approach is more helpful, though. Bus entries and ports exist as a sort of "virtual tunnel" which allow you to connect arbitrary nets to each side. It then performs a bunch of DRC based on your project settings and individual bus/port settings, to prevent improper connection. On the PCB side it understands the same concepts and facilitates the routing.

[@urjaman0]

For the 4-bit mux, wouldnt having just that one inverter make the non-inverted side act faster and thus cause times where both output enables are enabled and thus driver conflict? Having a buffer on the non-inverted path would make me happy enough about that, or just have a chip that does the 1-to-2 decoding (if easily available, i dunno). Or hey, if you want the 2 gates for the paths be the very same gate (same speed, less parts), they could be XOR-gates with one side tied to 0 and 1 for non-inverting and inverting respectively.

[@lawrencemanning]

That use of an XOR gate to even out the latency on both paths is neat. Slightly more troublesome construction if you want to use single gate packages. Would be interested to hear from Robert if latency matters here.

[@urjaman0]

Note: After applying one google search, i found out there exists a suitable 1-to-2 decoder in 6-pin SOT-23 (it also has an enable): 74LVC1G19

[@RobertBaruch]

That's a neat idea!

[@tomaspecl1082]

I know you can buy quad 2-1 mux chips but I don't know if the logic family you are using has that. Wouldn't that be better than building your own? It could be faster maybe. And definitely smaller.

[@PETMK]

What about single 74x257? But there's a question why to do it when it goes from the ROM that has an output enable... If the muxed busses goes from the same memory chip it can be swithed by the invertor (74x1G04)...

[@havresylt]

Bless you!

[@RobertBaruch]

Professional video editor here.

[@PETMK]

Maybe stupid idea but.... What if you use Z bus as the memory read data bus, Y bus as the memory write bus and the memory address and X as the memory address bus? I think they are free on the fetch phase, the X goes to the ALU to increment the address (by 0 or 4 - switched by just a constant on the Y bus on fetch ) and the instruction can be fetched from the Z bus... It may save a lots of chips and connectors

[@wChris_]

Well you could just record in 4k and let youtube do the down scaling to the other resolutions (also you are already doing it by recording in window mode)

[@lawrencemanning]

The one downside is it would make it really hard to watch on a phone.

[@PETMK]

There's another question. If we have eight registers in paralell how it know which one should put its content to the output? I don't remember how it's solved on the card...

[@madhusiddalingaiah5301]

Either multiplexers or tri-state buffers are typical. Tri-state buffers are easier to extend with discrete logic, e.g. add as many sources (registers in this case) as you like. There are no tri-state buffers internal to FPGAs or ASICs, so you would use a MUX and let the compiler deal with it in that case. In the DTL days, you could just wire-OR outputs. That was a selling point of DTL, even though it was slower than TTL. I never actually used DTL, but there's still some literature out there that talks about it.

[@PETMK]

@@madhusiddalingaiah5301 I kow how it works but there is a card taht contains a mux on the input and then some flip flop with tristate output. Let's have eifht of them in paralell with different input mux select. But we also need to read the data from flip flops and question is how he handle output enables so iit seems the outputs are joined together. It would be bad if you had PC, SP and other registers in same time on the same bus...

[@xxleite]

1:17:09 salud !

[@RobertBaruch]

Ha ha, oh no, I forgot to edit that out!

[@ancapftw9113]

I think it's pronounced "key cad" not "kie cad".