Memory Packaging Challenges for a Growing Market

The semiconductor memory market exceeded $128 billion in 2020 and is expected to grow at a compound annual growth rate (CAGR) of 7.8% from 2021 to 2024. Increasing demand for storage and high-performance memory in applications such as artificial intelligence (AI), machine learning and processing storage are driving long-term growth in the market. This video will highlight the key challenges encountered in packaging next-generation memory devices and some of the technological developments required to address them while considering performance, cost and yield.
Development in silicon design and wafer fabrication to meet increasing demands for higher memory density, higher bandwidth, lower power consumption and multiple functionalities introduces unique technical challenges for memory packaging. At the wafer fabrication level, the number of 3D NAND memory cells stacked is increasing. This causes a buildup of thin-film stresses in the wafer and die while increasing the amount of residual material in the saw streets to interact with the dicing process. Increasing memory density at the package level is achieved by stacking up to 16 or more memory die that are ultra-thin to maintain package height requirements. This combination of higher cell stacks and thin die, down to 25 µm and below, increases the risk of die cracking during dicing and assembly. To mitigate the risk of die cracking, dicing methods have been developed to increase die strength by minimizing damage to the die edge and removing the material in the saw street with laser grooving. During die-attach, specialized thin die kits are used with needleless pickup tools to minimize stress. To further reduce yield loss, automatic optical inspection is available to identify die cracking.
Integrated devices such as solid-state drives (SSDs) and consumer System-in-Package (SiP) modules also provide unique challenges for package design and assembly. Maintaining a small package footprint requires higher stacking and reducing the area used for wire bond fingers and passive components. One option for achieving this is including a flip chip controller die under the memory stack which drives the development for increasingly tight design rules and the implementation of film over die (FOD) or spacers over the flip chip controller.
Finally, achieving high quality and zero defects requires manufacturing processes that provide unit-level traceability throughout all assembly and test operations. Automatic inspections at the wafer and packaging level are utilized to detect die cracking and other assembly-related defects. Additionally, engineering data analytics are used to improve quality and performance while providing robust process capability with a focus on zero defects.
Presented by Knowlton Olmstead, Sr. Engineer, Memory Product Development at Amkor Technology
Originally presented at IMAPS Symposium 2021, October 2021. Visit Devicepackaging.org for details about next year’s Conference.