Nand2Tetris StudyAlong - Basic Logic Gate Design

[@netanelkaye3014]

why no canonical logic for Dmux gate? How did you know to go straight to diagramming the logic gate?

[@studymasterguide]

Shouldn't we be using only NAND to implement them??

[@famreno5132]

why do you stopped uploading videos

[@rnd_penguin]

I was gonna comment the same thing

[@itstoogooditswaytoogood3211]

"If you want to see if you can minimalize it at all, you can't." Yeah you can, by a large margin too. You can do an XOR gate with 1 NAND, 1 AND, and 1 OR (which is 6 NANDs). You did it with 1 OR, 2 NOTs, and 2 ANDs (which is 9 NANDs). Also you could have designed yours without wires crossing. You can quite easily do the boolean to see the minimalization by just doing: a'b + ab' = (a'b + ab')' ' = ((a'b)'(ab')')' then distribute to get (a'b' + ab)' = (a'b')'(ab)' = (a+b)(a' + b') = (a+b)(ab)' and i think you can actually do it with like 4/5 nands, which would be less than half of what you have but the 5 nand version has less of a propagation delay apparently. i don't know how to find the 4/5 nand versions using boolean algebra so i didn't bother with those

[@nesa6582]

Ive done XOR with 1 NOT and 3 NANDs. Which is 4 NANDS.

[@masui91]

thank u. perfect for me.

[@jaybirdcook]

Great but too quite.

[@xedover]

ah... you meant "quiet"

[@rnd_penguin]

yeah the volume is low

[@xedover]

your NOT diagram needs a bubble on the end of it, otherwise, its just a buffer that doesn't flip the value. (and your video volume is way too low... can barely hear it)

[@xedover]

your XOR gate diagram is wrong too... you've drawn a NOR instead. The XOR has no bubble, and has double curved lines

[@xedover]

dmux diagram is also wrong -- no bubble, and flip it left to right