VHDL vs. Verilog - Which Language Is Better for FPGA

[@shwetasharma3263]

I have recently came across your channel and i would say every video is very informative and practical too.thank you for sharing your knowledge and looking forward for more FPGA videos .

[@tinori1838]

I really liked how you showed pros and cons for both and i like your conclusion. When it comes to programming languages a lot of people are pretty emotional but this was just a very good explanation.

[@godfather7339]

Very much agree on the emotional part.

[@cosmofic4270]

It's 7 year old video and I'm watching in in 2024 and starting my journey now . 🙂

[@salmankhan-yw8oc]

Thank you so much for putting this video. And it feels like knowing one language is enough for a fresher.

[@hmdz150]

As a long time C programmer I have an easier time doing HDL coding using VHDL. Coding HDL requires a totally different mindset compared to coding software. That is why Verilog is confusing for me. It doesn't let me think free from software mindset.

[@hanniffydinn6019]

h zed but then he said Verilog is more c like...... Wow how confusing

[@mzamroni]

me too. I chose to use vhdl in 2002 when creating USB hub controller for bachelor degree final project. shh, each test cycle took 10 minutes to compile and 5 minutes to simulate in Pentium 3 computer

[@gabemvp]

Right to the point!

[@jeremiefaucher-goulet3365]

LOVE this answer. I was looking for something like this. VHDL seems like the right choice for me to begin.

[@dincerekin]

I like verilog cos it's similar to C lol. & should be AND instead of concatenation. Plus verilogs literals make more sense. E.g. Data

[@martandrmc]

I am a university student in Greece learning computer engineering. I had learned (System)Verilog from an American friend prior to starting my courses and then I was surprised how little relevance it had. I asked my professor and he told me that "the trend" in Europe is to use VHDL and in America to use Verilog, as you basically said. He also pointed out that "the trend" also concerns FPGA vendors, with European academia preferring Xilinx and American preferring Altera. Personal biases aside, I still don't understand why this skew even exists, but I ended up being completely misaligned with it, having been taught by an American but residing in Europe. Now, about my opinion on the matter... They had us implement a subset of MIPS in VHDL and that was the first time I had to get hands on with it, which made me directly compare the two languages, and ever since I have been swimming against the current so to speak. I really don't like how (in my opinion unnecessarily) verbose the language is. I advocated for Verilog instead, pointing out C's influence over the language, since they had a C course on the first semester. But alas...

[@Slicudis]

VHDL = Hell of pain and suffering

[@vonnikon]

Verilog is being more actively developed, with new features added first in Verilog and years later in VHDL. One example in particular: It is possible to represent a databus like AXI as a single port in Verilog. While in VHDL your AXI bus will be 25 individual ports. This feature is coming to VHDL as well, but it takes years for it to happen...

[@derekonxbox]

3:59 Is there a train passing by? I swear i hear a graham white e-bell ringing and a loud rumble in the background

[@burgerking220]

My Verilog professor said Verilog was the best and was not bad like that clunky mess of a language VHDL. My VHDL professor said Verilog is an ancient language no one uses

[@bertcuzeau7800]

Nice intro for beginners. I would just add: * ASICs are in Verilog (especially close to back-end) * If Digital Design is going to be your job, then you need BOTH ! * Neither are intuitive nor very simple to learn, HDLs are another breed as compared to programming languages. Self-teaching HDLs is not a professional nor reliable path. * AND there is a huge Game Changer now : SystemVerilog which is the language of the next 20 years (if HDL and FPGAs don't die in between). Since SV is a superset of Verilog, so today I would rather suggest learning Verilog rather than VHDL, even if (being located in Europe) I wrote more VHDL than Verilog since 24 years. Bert

[@johnmarston7005]

Hi Bert, could you please write something more about self-teaching HDLs being not a professional nor reliable path? What's the best way to learn HDL then?

[@ahmadalastal5303]

@@johnmarston7005 I have be studying Verilog on my own since 2018 and I found the best way to teach yourself is by doing small projects and see examples, which is pretty much the old fashion way, it is now 2021 and my skills are really advance, I did dozens of project and I get better and better after each project, I work as a c++ developer since 2019 and continue my FPGA journey, I searched for FPGA jobs but they keep rejecting me and say nothing about why, maybe I should also learn VHDL, I am electrical engineer by the way

[@rays14ful]

I worked in both Silicon Valley (Apple) and defense (Raytheon). In Silicon Valley I did two FPGAs. Very tiny little FPGAs. Both in verilog. In defense I did a whole lot of FPGAs and huge designs. Entire radar processing to controls. All in VHDL. What I learnt was that the use of FPGAs in Silicon Valley is very low compared to defense. The bulk of FPGA work is in defense. I Silicon Valley most products are consumer products and se has to be small and cheap and power efficient. So any FPGA design is quickly made into an ASIC and the work continues in C.

[@lawrencemanning]

I use VHDL in my hobby projects. It is certainly much more verbose. I like it for this reason, oddly. But I'm very keen to learn Verilog, especially as I want to do this for a living. One nice aspect is it's apparently possible to mix different languages in the same design, so I'll have a go at rewriting some bits in Verilog. Maybe I'll end up liking it.

[@whyareyoulookingatthislol]

AFAIK VHDL is used by a lot of govt positions

[@spiderrobotheavyduty5028]

very good presentation ,thank you

[@DanEllis]

I started learning with Verilog. I think I'll end up switching to VHDL eventually, because strong typing is good. I've already experienced errors that slipped through in Verilog.

[@martinwashington3152]

Very nice introduction to the difference between the two HDLs, thanks for taking the time present an upload :)

[@vit777vit]

VHDL and Verilog are hardware description languages but not sftware programming languages. So they are the congenerous semantics. Hence we make schematic diagram using verbose languages instead graphical representation of a dot. But, easier to say 'horse' then making its drawing. And this case, I suppose, that Verilog and VHDL languages have to draw the same device (spherical horse in vacuum) for all supported FPGAs.

[@ashishsontakke4040]

thank you sir....very helpful..

[@مروانعبدالخالقذنون]

Dear Sir Thank you very much for your helpful information. I want to work a project of tracking of moving target in real-time using FPGA. What is your advice to me to use VHDL or verilog? Thank you.

[@KingDuken]

I think Verilog is a good start for anyone who is starting and just learning any hardware description language. VHDL is more for advanced users who want their code to be more literal and accurate. There's really no "better" language. It really comes down to what you think is easier and what will get the job done according to well thought out specifications.

[@gmortimer20031]

I prefer the pedantry of VHDL, which as a beginner constructing a huge project (which occupies 70% of a Zynq 7100) I find somewhat helpful. I can use .v and .sv, though, too. The version of Vivado I use (15.4) sometimes gets confused when I construct a piece of custom IP, and if the piece is simple, and it defaults to .v, then I use it! For anything of substance I use VHDL.

[@agstechnicalsupport]

A good, unbiased comparison of VHDL and Verilog.

[@mzamroni]

vhdl vs verilog done. next, tab vs space

[@Nandland]

2 second video... space. mic drop.

[@lawrencemanning]

Am I the only one left who prefers tabs?

[@LinhHoang-zi9mt]

@@Nandland vim vs emacs

[@ksbs2829]

@@lawrencemanning yup tabs all the way! Also tabs every 8 columns. No debate. :-)

[@ashwinikurhade6041]

Can anyone suggest a good book for Verilog?

[@riddhipadariya7517]

Which book is best to learn FPGA for practical use? Please provide me a suggestion! Thanks.

[@Nandland]

I don't know... I never found a good one, which is why I created nandland and these videos in the first place.

[@cheebeez]

Digital Design and Computer Architecture by David Money Harris and Sarah L Harris

[@rafaeltmbr946]

This book is really good for systems design, it shows you that digital design it pretty straightforward.

[@metildsa6138]

"FPGA prototyping by vhdl examples". Pong P. Chu

[@omari4625]

Riddhi Patel vhdl for engineers Kenneth short is a good book

[@MilanKarakas]

I am just beginner in FPGA world. And my firs impression that VHDL is what I want to use.

[@ΝικΝοκ]

to me someone should know both. maybe master one but both are usefull. i think verilog is more straightforward and simple.. modules are just simple and nice inputs and outputs seem straightforward. but its my oppinion (i starded with verilog)

[@baconsledge]

Good vid!

[@windydoo8618]

Appreciated.

[@wilsonlopez697]

Let's say Verilog is like JavaScript, right? 😂

[@vikrantthakur7482]

Hi, I am undergraduate engineering student from India.Actually, I have worked on VHDL earlier.So according to you if I want to strike to work in industries or willing to pursue research. Should i go with depths in VHDL or should i also start learning verliog?

[@mzamroni]

I prefer vhdl but any of them will do. hdl software can combine component created using different hdl

[@SeverityOne]

I had an idea the other day: design an HDL based on lambda calculus, so basically a functional programming approach.

[@luuclucas]

Already exists, I am currently doing my master thesis using Clash, which is based on a subset of Haskell.

[@godfather7339]

Really cool, maybe there is a lisp library to write hdl?

[@nandsingh4669]

ok I am going for verilog thanks sir

[@6s6]

awesome vid

[@HamsterSnr]

Learnt VHDL way back in ‘92, and still using today for FPGA. But it seems all the example designs provided by the FPGA vendors are written in Verilog 😡

[@hrnekbezucha]

Interesting, I looked up local search results on trends and VHDL is very consistent in popularity, while Verilog jumps in and out of favour all the time.

[@gabrieldegret1359]

FOR VHDL !

[@yasmeen2173]

hello have you an email can l contact with you ? because I have a project and I need to help to do my project please. my project made by verilog language .

[@Wren6991]

As a counterpoint to those trends: I do ASIC design in the UK and use Verilog (and occasionally SystemVerilog) exclusively. All of my colleagues write Verilog. One of my colleagues came from ARM, where Verilog 2001 is apparently the main design language. I also work with several contractors (who do, for example, FPGA integration to help with our soak testing), all of whom mainly use Verilog. I am wary of using google trends to predict what HDL designers actually use.

[@Nandland]

Yes, if the company or industry you work in uses one language more, definitely stick to that one! The google trends was used to highlight the regional differences and give people at least a place to start.

[@Wren6991]

Okay! Thank you for the response :) I love what you're doing.

[@Wren6991]

I was looking at your Go board, and it seems like only the HX1k part is available. Do you have (or have plans for) an HX8k-equipped board? I'm playing with IceStorm at the moment, and Go board seems a lot nicer than Lattice's breakout board.

[@Nandland]

Thanks! It has a lot more features and tutorials, which was what I was going for. I don't have plans for 8k at this time, but if there was ever a ton of interest in such a product I could look into it. Thanks for the suggestion.

[@DoktorSchaedel]

Verilog prof: VHDL is trash VHDL prof: Verilog is trash

[@IngersollMaria-z9s]

Anderson Gary Robinson David Harris Edward

[@4explore]

In defense and avionics, it's almost exclusively VHDL.

[@MrSapps]

Great Briain?? lol

[@DanEllis]

Great Bri'ain. It's a glottal stop.

[@BettyClark-r3h]

Hall Linda Anderson Richard Moore Mary

[@slap_my_hand]

Seriously, what idiot thought it would be a good idea to make these two languages the global standard? Verilog and especially VHDL are just a mess of superfluous keywords. Why not just make everybody's life easier and create a language with a minimalist syntax?

[@BettyClark-r3h]

Clark Margaret Clark Thomas Clark Scott

[@stephenholstein231]

From a software background, VHDL looks superior. After seeing languages like C and C++ that tried to make things "simple", verilog and system verilog seem headed down this dead-end. New languages like Rust force the user to be aware of all the hidden gotchas that crept from the early days into new languages. For all the syntactic goodness of verilog it carries a lot of hidden gothcas.

[@MaxwellBerkeley-m8k]

Nitzsche Turnpike

[@71GA]

VHDL's syntax sucks... but it is much better....

[@varunmajji6514]

verilog is used in every semiconductor company,

[@jeanperruchoud6763]

Both languages are potatoes, don't trash your time learning them, instead look to the opensource alternative HDL : - SpinalHDL - Chisel - Migen Really, VHDL and Verilog are just OK as netlist language, as soon you want to advanced things they become copy/past non reusable nightmare unless you use dirty languages workaround.

[@aaronchamberlain4698]

This is probably some of the worst advice for someone looking for a job. I searched for the phrases "Migen FPGA" on indeed and the same for all the languages you listed. I got 0, 2, and 0 job results respectively. Chisel only had 2 for an internship that was duplicated and it was a bonus requirement with any other HDL as a requirement. VHDL had 1,138 PAGES of listings and Verilog gives 1,619 PAGES. Huge difference in job prospects. I'm not sure I disagree from a language perspective since I have glanced at Chisel because I was interested in RISC-V and see it's value. It may have even more job value in the future as RISC-V takes off, but if you want to a job *today* learn Verilog/SystemVerilog or VHDL. EDIT: This is true for all other regular software languages as well. Sure JS is a pretty ugly language, but there are a ton of jobs...

[@jeanperruchoud6763]

Hooo about RISC-V stuff, check out github.com/SpinalHDL/VexRiscv Probably the best open source RISC-V for FPGA, and written in one of those industry ignored HDL : D

[@aaronchamberlain4698]

Jean Perruchoud wow that project does actually look interesting. Happen to know FPGAs that’s tested on? At one point they mention it running on an Artix7, and 3 different cyclones but that’s it. Been meaning to pick up an Artix board for when I’m not at work so I’m still using Spartan 6

[@jeanperruchoud6763]

Was physicaly tested on ice40 hx8 break board, DE0-nano, DE1-SoC. But the RTL is compatible to xilinx stuff. I know that some people are using it on Artix :) The metrix that you can see on the readme are synthesis results.

[@heater5979]

I would not go as far as to say don't learn Verilog or VHDL. But SpinalHDL brings HDL up to a whole new level of sophistication. Like going from assembler programming to C. If you really want Verilog of VHDL then Spinal generates both of them for you to admire. They are the assembly language on the way to being a bitstream for your FPGA or chip design. With Spinal's use of Verilator it makes it dead easy to create test benches. There is a reason the kids at Berkeley are working their RISC V magic in Chisle, which is very similar to Spinal.

[@stefanogrillo6040]

Explanation is good but nobody want to see unpretty streamers face! sry bro.