Pin Diagram of 8085 Microprocessor (𝜇P) - Part 1

[@surya.6907]

you said rst 6.5,7.5,5.5 are generated by software instruction but in google it says they are hardware interrupt.

[@Xyzengineer]

Hello sir, i have few doubts. what does the clock frequency signify here and what is natural frequency and why is getting reduced to half of it when voltage is applied at X1?

[@tabindashafi4983]

Thanks a lot sir ...

[@cck0728]

Thanks...Can anyone tell the difference between "maskable" and "non maskable" interrupt? Thanks.

[@kephamtran1252]

i guess it is just "intended" and "unintended" interrupt with levels? "unintended" interrupt tells you to immediately stop the action taking now to do the new given instructions right away unwillingly. "intended" interrupts are done by programmers to do the new execution after finishing the current task.

[@kephamtran1252]

"Maskable interrupt is a hardware Interrupt that can be disabled or ignored by the instructions of CPU. A non-maskable interrupt is a hardware interrupt that cannot be disabled or ignored by the instructions of CPU. When maskable interrupt occur, it can be handled after executing the current instruction." another source says

[@cck0728]

@@kephamtran1252 Thanks for your kind explanation...

[@shooksyt6306]

First