nMOS Inverter (Basics, Circuit, Working & Voltage Transfer Characteristics) Explained

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who is here before their semester exams??😂

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1 day before exams ❤

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​@@prathamgoel3386 Abe ja ymca ke student

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Me

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Me

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[@abhishek17092]

Thank you sir. Your explanation s are very good.

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Great lecture sir ,Keep up the Good Work! .Best Wishes!.

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[@ganeshvhatkar7166]

Very much helpful sir ❤️ thank youuuuuu sir ❤️❤️❤️

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[@ganeshvhatkar7166]

@@EngineeringFunda sure sir I had share to my college group , really helpful sir this series 🙏🙏🙏❤️👍

[@JitendraPatel-ej7xn]

very good explanation.

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Your positive comments motivates me. Teachers like me just wants positive comment from student. Love from you guys means a lot to me. My goal is to create largest community of engineers in entire globe. Please help me by sharing this playlist with your friends.

[@naveenyadav3489]

very informative...❤️❤️❤️

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Very nice video sir 👍👍👍

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[@siddhantrana6410]

sir pls write D in proper manner in whole video , I was confused that its VP not VD

[@somnath3986]

@@siddhantrana6410 that was a very rude way saying it to a teacher

[@nikhilKumar-ui8bs]

Sir please make more clear transfer characteristics.

[@Skall-ex]

I can't quite hear what you are saying at 7:54. Is it "lambda capacitance"? Why is that capacitance added? Very good video otherwise, best explanation I've come across.

[@yogyaarora2248]

thank you so much :)

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Thank you.

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[@harshithabr1951]

thank you so much for your amazing teaching if you can teach asic for mtech to do consider

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Noted ✅

[@bhanugudur]

Why you are writing Vdd as Vpd at 3:06

[@swatichauhan2106]

sir at 14:11 the slope should be positive no because it is increasing ? please clear this doubt

[@EngineeringFunda]

It is Negative. / this is positive slope \ this is Negative slope

[@swatichauhan2106]

@@EngineeringFunda ok sir thank you so much

[@arijitkumarpandab4232]

good good highle recomded

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[@diyafavas_official7012]

Sir please explain about PMOS inverter

[@Siggfuggggg2000]

Does it matter if mosfet is in linear or saturation when Vout is low voltage? Because you could pick a resistor that would make either of those the case

[@EngineeringFunda]

Working of any device is not only depends on one condition at output, we should analyze both conditions at output. Regarding zero logic at output.... you can see the region in which NMOS and PMOS is shown.

[@vidyakoul570]

Thanks

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[@amolbansal6769]

Sir please upload your notes too

[@Mindfacts432]

Sir... Here how to solve expressions for vil vol vih.. plz convey sir

[@prateekgupta7845]

Sir, i followed this whole cousre, ,, but can't understand these graphs.. 😧

[@agentwalker7045]

Why there's a negative slip i.e -1 ?? can someone explain please?

[@subhadeepbhakat7765]

Sir plzzzzzz make vdos microprocessor 8086 It's truly an earnest request to you sir

[@syedamariabatool6353]

VOH again in the bottom or here it should b VOL because output is low here

[@EngineeringFunda]

It is perfectly correct

[@TANIAAKTER-t9r]

Which book is followed?

[@EngineeringFunda]

In 1st video of playlist, it is mentioned

[@shrishtiswaraj3797]

sir vdd or vpd??

[@EngineeringFunda]

Vdd

[@joyboy00008]

Need more clear explain actions,,I watch this 5 time still I didn't understand

Sir, from where we can get these notes?

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@@EngineeringFunda Sir, i think these notes are not there. In VLSI section, only 1 MCQ sheet is present sir.

[@preetiraote2891]

why is dvout/dvin = -1 ?

[@shrishtiswaraj3797]

where is the next video sir as you mentioned in the last 🥺

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See playlist of vlsi

[@ndewangan2053]

Nit raipur me ek mishra naam ka teacher yhi padhata h class me samjh nhi aata lekin yha aa rha h pta nhi kaise

[@adeddy8138]

V ds is drain to source or drain to substrate voltage and Vgs is gate to source or gate to substrate voltage?? I am having confusion plzz help sir!!!!

[@EngineeringFunda]

It is with respect to source

[@tanmaymishra8169]

amazing video , but why have you locked some videos for 200 Rs sir , its not a good stunt , not expected form you

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[@luizvision478]

OK ...PLEASE PUT LEGENDS PORTUGUES AND INGLES AND YOUR LAMGUAGE . ALL 3 OPTIONS

[@shrishtiswaraj3797]

vdd is called what sir???

[@EngineeringFunda]

Supply in CMOS, as you see Vcc in transistor

[@AKLESHKUMAR-dr3vm]

sir where is derivation of VoL,VOH, VIL, VIH ;

[@Siggfuggggg2000]

There is no derivation it’s just convention and everyone went with it

[@AKLESHKUMAR-dr3vm]

@@Siggfuggggg2000 you know without derivation we cant gate anything ,

[@Siggfuggggg2000]

@@AKLESHKUMAR-dr3vm my Professor in college just told me the other day this is the case (what I said earlier)

[@AKLESHKUMAR-dr3vm]

@@Siggfuggggg2000 okk but my professor is not same as your professor , u got it . Bcz without derivation you not clarified, where VOL , VOH, VIH , VIL exist, then other thing how you find it out noise margin , and other type of inverter like cmos , resister type of inverter an nmos-pmos. i hope you understood , what i want to say.

[@Siggfuggggg2000]

@@AKLESHKUMAR-dr3vm from what I understand it’s the same for all inverters but the slope -1 points is just a convenient cutoff somebody chose a long time ago and now it’s convention

[@loner2798]

Kang?

[@aeroasss9740]

Bro You made a very pathetic reason behind zero gate current!!!!