OS Context Switching - Computerphile

How does an operating system juggle different programs? Dr Steve Bagley explains Context Switching.
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This video was filmed and edited by Sean Riley.
Computer Science at the University of Nottingham: bit.ly/nottscomputer
Computerphile is a sister project to Brady Haran's Numberphile. More at www.bradyharan.com

[@MichaSpielt]

Strange how you always upload these videos just after I wrote my exam about the topics

[@vipsylar6370]

Hahaha

[@TraitorVek]

Academia

[@nicholaszenos6180]

I have an os exam that covers this stuff next week so lucky me

[@tritrinh568]

May I read? :)

[@fletcherreder6091]

How did you post this from a week in the future?

[@proudsnowtiger]

Once did a pre-emptive (interrupt driven) multitasking teeny tiny kernel in Z80 that could do a complete process switch in < 400 T-states. A thing of beauty. This was about four years after anyone would want a multitasking Z80 system, so the project got canned, but just for a moment is was deeply satisfying.

[@blahchop]

Nice

[@lucidmoses]

Back in the DOS - 8088 days I did my own cooperative multi tasking inside a C program by allocating memory for another stack and doing some fancy fiddling with the BP pointer and such. It was a supper fast context switch. Basically just push the BP to the appropriate stack and then return. The return would return you to the other thread.

[@Chriva]

Never done anything that advanced but I must admit I've cheated with the return-trick on a few processors to save space. Really neat to branch that way when you have full control (obv not convention conformant) :)

[@lucidmoses]

@@Chriva Yeah, this level of tinkering isn't really needed any more.

[@frechjo]

@@0x90h He said "cooperative multitasking", you are thinking preemptive multitasking. It probably switched on specific calls, no need for timer interrupts.

[@mikefochtman7164]

Learned a lot about this topic on SEL's MPX OS. Combined real-time 'hard' priority switching and 'round-robin' priorities. Was pretty interesting setup and could 'peek' in various OS structures.

[@nico-s29]

Props to the guy animating the drawings

[@trevinbeattie4888]

Will you be doing a video on virtual memory management? This was a big step in processor evolution from the MC68000 to MC68030 (and probably other CPU's ;) ) which has a direct relationship with context switching, as the OS not only needs to swap the register set but also the page translation tables.

[@joelvanin]

Excellent time I am just learning it this week, love this channel

[@SupaKoopaTroopa64]

This is the Computerphile video I've always been waiting for!

[@artiem5262]

In the DEC VAX instruction set, there are (privileged) instructions for saving process context and loading process context. At least for the first few releases of DEC's VAX/VMS operating system, there were two instances of save process context, and one instance of load process context in the OS core. Yes, VAX is probably the epitome of complex instruction sets!

[@MrMalchore]

These videos make it sound so simplistic. But if you tried to read Linux source code...grab the asprin.

[@skrrBOP]

This video is explaining the simplest context switch, it's obvious that Linux is much more complex.

[@erikawwad7653]

use an ide, they make it so much easier

[@SimGunther]

@@erikawwad7653 To load in that much source code? Better luck with pen and paper hand debugging than loading in 3GB of source code with all that indexing!

[@erikawwad7653]

@@SimGunther I'm sure lazy indexing is a thing

[@dsedchenko]

Thank you for the video! Can you make please a video about how protection rings and how process isolation is working?

[@cmdlp4178]

Could you go deeper into the interrupt mechanism, which was mentioned at the end. I want to understand what happens on multi core processors

[@dannynewman82]

Good vid man. Really informative 😀

[@franchello1105]

I built something like this for my final project in Operating Systems in college.

[@lidorbenshimol1838]

hello, I would like to know if Threads effect Context Switch Also, if they do, does it mean that the more Threads there is --> More Context Switch will be?

[@ailuros_]

I would love even more if this video had english subtitles :| btw, great video! thx

[@pierreabbat6157]

I've seen the way to save and restore context on the CDC 6600 (18-bit address registers, 60-bit data registers, no stack). It is quite involved and tricky. One register has to be saved a bit at a time before it can be used to save the others.

[@perschistence2651]

I did not understand some things. What is the difference between "SWI 3" and "SWI 4"?

[@marlandkennedy7747]

Where were you when I was taking operating system class. Well you might not have been born when I took it.

[@EvertBorghgraef]

Which is the original video that he is referring to in the beginning?

[@lawrencedoliveiro9104]

9:09 You’ve already said that the registers seen by the OS kernel are not the same as those seen in user mode, even though they have the same names. So presumably the OS has access to special instructions for accessing the user-mode registers, in order to do this save/restore (and no doubt other purposes like obtaining arguments and returning results for SWI calls)?

[@zeektm1762]

The same registers are being used. I'm unsure of his explanation. The same registers are being used throughout however the previoisly running tasks has a frozen copy of the state the registers were in at that processes time stored in memory.

[@lawrencedoliveiro9104]

No, the registers have the same names, but kernel mode has its own separate registers. This avoids having to save/restore registers when switching modes.

[@phoenix2464]

Dr Steve, always making making us hungry for more. literally.

[@crtxl]

A like from me because of the Ataris in the background.

[@JerehmiaBoaz]

"APR RO, iString" should be ADR R0, iString

[@IceMetalPunk]

Thank you. I was confused; I was like, "Wait, what's the APR opcode? How is it different from ADR?" I Googled it and couldn't find anything about APR, so I concluded it was a typo. But man, that's 3 minutes of my Googling life I'll never get back :P

[@HenryHoneyBadger]

Yeah saw this too, beat me to it.

[@blahchop]

@@IceMetalPunk lol

[@aVeryHandsomeWall]

I stumbled upon your channel and the name remembers me of sciencephile the AI :( But great video :)

[@su8z3r03]

Is context switching the same as process switching ??

[@BusAlexey]

I'm kind of new to this, but what if we have two video-playing programs running at the same time? by the logic that only one thing can be running, aren't we going to see constant glitches on both videos as it tries to do them?

[@Chriva]

Still switching. The hardware is using a lot of tricks (like buffering, dma, hardware decoding etc) These days we also have more cores that can spread the load and switching but it worked just as well on a single core back in the "stone age" :) Video isn't actually played frame-by-frame in that sense. Same goes for audio. Just imagine the micro stutters if you had to manually push a sample value 44.1/48 (or higher) thousand samples a second to the sound card/onboard audio :P

[@vincei4252]

There is process level context switching and thread level context switching. It is done extremely quickly so from a humans perceptual perspective you wouldn't notice. In a windowed OS having two games running in two different windows regardless of how many physical processors there are is perfectly fine. The operating system knows that there are two programs running and isolates them from each other.

[@myrrdyn]

Without considering double buffering and other tricks, a video playing at 60 fps means that you have 1/60 seconds = 16.6 ms to process one frame, so if your video decoder takes less than that there is no problem.

[@trevinbeattie4888]

Neither program would (or should) have direct access to the video hardware. That's one of the functions of the OS - to manage programs' access to devices. In a simple system, only one program would get to display its video and the other would block waiting for the video device to become available. In modern windowing systems, the display process (e.g. X Window System) has control of the video output, and programs send their video streams to it to arrange and display as the window system sees fit.

[@acommenter]

what is the video being referred to at 8:50-9:00 ?

[@James-ln6li]

I came here to ask the same question.

[@VivekYadav-ds8oz]

I've been persistently confused about how is an OS really written? malloc(), free() all call OS's subroutines to allocate space, the stack-heap architecture is also imposed by the OS, then how does one manage all this when they're writing the OS themselves? How do they allocate memory? How do they make space before their program starts (stack for temp variables and heap), if the language itself assumes this would be provided by the OS?

[@lapatatadelplato6520]

They would do much of that in assembly. In assembly, all one needs to do is define all of the memory to be an array you can allocate, and then switch control over to C. From there, you would write your own Malloc and free, and everything else. Lookup Baremetal programming in C

[@dariokartal9453]

That is one cool shirt! It's got spiraling galaxies, rockets, the planet Earth, Saturn, stars... I have a similar one with just random white dots, but yours is it.

[@LewisCowles]

Thusly describing the problem with context switching and maintaining hardware & software state parity in application layer, which is why kernel-space exists. Kernel space does not cleanly fix this, it just defers from program code, allowing it to be thinner and SWI {n}. By inferring that the driver will be better equipped than an application to maintain state we get less rigid applications which work across hardware due to conforming to specifications such as OpenGL {x} compatibility. Anyone using unsupported hardware on Linux, Window or Mac has seen the issues of this decision though. Things either don't work if you switch the focused application and switch back, or devices do not work, etc. HMP > SMP all day long

[@KangJangkrik]

Question: how does CPU store its context into HDD when S4 ACPI state (hibernate) fired?

[@gregoryfenn1462]

That’s way too specific; not related to this video. You had better just Google it.. maybe stack overflow can help you

[@KangJangkrik]

@@gregoryfenn1462 well... yes, but if I satisfied by google search then I don't have to comment here. And second, there must be a mechanism to store context state somewhere at swap region. So that still related to the video.

[@cmdlp4178]

Machine code, but also compiler builtins could be used.

[@peppybocan]

I wonder how is the context switching done on the real-time OS.

[@jdm8963]

I'm sure it will be in a simpler way to deal with time restrictions.If anyone can tell.

[@Chriva]

The usually use one of the chips timers to perform the switching. (notice how you rarely have access to all the hardware timers) :) I honestly don't know the details how they create threads and whatnot but the switching itself is usually triggered by a timer.

[@steefant]

it's not different apart from that the list of threads and PCB are/might be simpler. the process of switching context takes of course some time and thus increases the lower bound of reaction time the OS can guarantee. however, this is fairly fast in comparison to other more complex tasks of an OS. the timing of preemption can be controlled by setting up a timer if need be (e.g., to make sure a periodic task gets run/started at exactly its set period).

[@trevinbeattie4888]

The main difference is in deciding when to switch and which process gets priority. As mentioned in the video, ordinary operating systems can either switch when the application relinquishes the CPU or on a regular timer. Additionally, the OS may do a context switch in response to an interrupt from an external event, which can change a process'es state from waiting to ready. In a RTOS, emphasis is put on process priority in the process list, so if the highest-priority process was already running the OS won't switch it out; but if a higher priority process becomes ready, the OS will switch to it right away.

[@salerio61]

Why would you think it would be different? The hardware interrupt is the thing lacking on the Arduino :( I've 30 years as a design engineer on r/t embedded systems from the GEC4000 onwards if you want to ask. That processor was as real-time as it gets.

[@MrSigmaSharp]

Is this how hibernation works? If so how os preserves itself?

[@Xilefian]

I've been programming exactly this kind of stuff recently for an embedded platform

[@BankShotter]

That's really cool!

[@bytefu]

Some kind of Cortex-M, I presume?

[@konstantinrebrov675]

Can we have a video about FPGAs and how they work?

[@glynwatkins9968]

no interrupts in the program??

[@pfefferle74]

"SWI" is the software interrupt instruction in ARM assembly - the equivalent to "INT" in x86 assembly.

[@FredrikRambris]

Does CPUs generally have instructions for dumping and loading all registers or does the programmer need to write code to dump each register one by one?

[@schifoso]

For a context switch, the CPU or OS should be preserving the registerers. For function calls, the programmer must preserve register values that may be destroyed, unless the value is supposed to be destroyed such as when the register will contain a return value.

[@SethPentolope]

Generally yes, mostly. Sometimes some registers are expected to not be saved though, so in those cases you wouldn’t want to. Depends on the calling convention and sometimes veneers that the assembler/linker might want to generate and use for memory offsets. With the ARM assembler I am using currently, I can type “push {r1,r2,r3}” to push those three registers to stack (pop is the same syntax) and I can specify any number of registers for that to happen for. I think there is an x86/x64 instruction for it, but I don’t know it off top of my head.

[@GordonAitchJay]

With the Motorola 68k you can copy/restore all the data and address registers with one Move Multiple Registers instruction. For example: movem.l d0-a6,-(sp) ; copy to stack movem.l (sp)+,d0-a6 ; copy back from stack

[@Flankymanga]

Guys can you make a video about Formal methods in software development context?

[@casperes0912]

If you're interested in that you may want to look at CompCert, the mathematically proven compiler

[@vertexedgeface3141]

^ Also functional programming using pure functions.

[@ELYESSS]

I know this. I dunno why I am still watching

[@noizy514]

I want to eat jelly candies now. :(

[@rhoharane]

I also want that shirt.

[@olaff667]

very nice mdma crystals

[@iStormUK]

By eating the jellybaby he caused windows to bluescreen. Protip: Never eat those VXDs no matter how tasty they are!

[@albertbatfinder5240]

How does the OS do things (compare things, count, move things about, whatever) without clobbering a client program’s registers? I mean, the OS is just another program, isn’t it? Is it context switching itself in and out? How would it ever get back in, if it were out?

[@vk3fbab]

Depends on the architecture. In ARM the supervisor program or OS gets its own set of registers in hardware. In other architectures the OS might need to be careful by storing registers on entry. You could also hack by saying the OS uses these registers much like calling conventions for function calls. Context switching is similar to how function calls work on processors that stack registers for you just different processes.

[@schifoso]

That's what the whole video is about. The registers of the program/thread are preserved in memory before the values of the new processors registers are loaded from their saved state.

[@wmrieker]

timerinterrupt: push registers on stack point a register to current pcb (current pcb held in static memory location) save stack pointer in that pcb you now have all registers to figure out which process is next point a register at new pcb (same static memory location as above) load stack pointer from that pcb pop registers from stack rti

[@AstAMoore]

The TL;DR version: PUSH AF PUSH BC PUSH DE PUSH HL . . . do some stuff . . . POP HL POP DE POP BC POP AF RETI

[@janhetjoch]

TL;DW*

[@BicyclesMayUseFullLane]

lol Z80 now do ARM and amd64 😁

[@az09letters92]

That's just a simple interrupt handler... not pre-emptive multitasking.

[@HenryHoneyBadger]

ARM doesn't have the concept of push/pop/return instructions. It has pseudo stack operations.

[@martin.pokorny]

Hah, I recognize this. I'm learning Z80 assembly (seriously). I'm new in assembly and Z80 is relatively simple.

[@MrSpikegee]

@3:24 small typo: APR op-code instead of ADR

[@MatthewHarrold]

The Doctor played by Tom Baker has a huge influence on modern culture. I don't care if it was intentional or not. The influence has been detected, it's out there, there's no putting it away. Lovely.

[@DrSteveBagley]

You may well think that, but I couldn't possibly comment…

[@MrXoury]

The missile knows where it is . . .

[@RustyTube]

Yes, but you not only have to save/restore R2 but also D2. Otherwise the Death Star will explode during the context switch.

[@sonisphere098]

yes

[@romanabeiro9181]

i need subtitles, por favor

[@Vinxian1]

This video would have been great before I had to make a port for my microcontroller in FreeRTOS ;P

[@quill444]

It resembles simple Push & Pop Stack within plain Assembler or Machine Code. - j q t -

[@aleshiukas]

Why NOP ?

[@iabervon]

I think he's got the NOP in the wrong place. I'm pretty sure it's supposed to be after setting the PC to the task's next unexecuted instruction, and is there because the processor loads the next instruction while it's executing the current one. With a branch, it discards the instruction that it loaded while it was executing the branch, but just setting the PC misses that hardware, so it's going to execute the instruction from the OS code that's right after the context switch code as if it were an instruction of the program it's switching to, while it loads the next instruction in the program. So you just make that instruction a NOP, so it doesn't do anything weird.

[@JPBennett]

Related and interesting: Hyper-threading (SMT) is essentially hardware accelerated context switching.

[@Chriva]

Nah, they're letting other threads execute instructions with unused parts of the chip (almost impossible to use every single part of a processor with one single instruction). While one is doing an addition, another thread could use the fpu or read from memory etc

[@philsburydoboy]

@@Chriva Yeah, Christian is right. Hyperthreaded CPU "threads" have their own independent set of registers, but share a set of instructions. There is just some logic implemented to make sure they aren't ever running the same instruction at the same time. You might be thinking multi-threading, but that is only sometimes true. The amount of context switching you have to do is (naively speaking) #threads/#CPUs. If you had 4 threads and 4 CPUs, you don't need any context switching.

[@cfsmart]

Called ARM Assembly Language.

[@ethandavis7310]

says he's going to write in machine code, begins writing assembly

[@jimjohn2652]

So, if all the 'simultaneous' processing are being done by the OS, then in principle it should be possible to compile any sort of heavy load program into a bootable image that will execute without any of the OS interrupts, random memory accessing and switching. I wonder how much faster a given program would run in this scheme compared to it being run from an OS.

[@damilolarandolph8523]

I was looking for javascript vids and ended up here, I feel sad now

[@strategist32]

*clicked on video thinking it was talking about adjusting from the feel of one OS to the feel of another OS on the fly* I see now that I was very wrong.

[@TraitorVek]

R1 Has No Choice

[@vbnm193]

Just learned this in uni lol

[@Chriva]

You can change the timer on Linux. No idea about Windows and crapOS. I wonder how much performance is wasted on the switching? I mean it has to dump register contents and whatnot on the stack to be able to restore it. I know you can save a lot of performance with low-level stuff by minimizing memory access and branches. would be fun to get a benchmark of a desktop system somehow

[@ShinyQuagsire]

I believe there was a paper which estimated about 20% performance loss due to context switching. Though, it depends on the threading model and number of cores. A cooperative threading model would prevent a computation-intensive task from being interrupted and more cores decreases the chance of cores being congested and/or caches having to be flushed/invalidated to transfer the thread to a non-busy core.

[@casperes0912]

Why would you mention Windows twice?

[@Chriva]

@@casperes0912 You know what I meant, iSheep ;)

[@Chriva]

@@ShinyQuagsire Do you perhaps know of where it can be read? (I believe you, it's just I'm not having any luck with Google lol) I find this stuff interesting to read about :)

[@steefant]

desktop operating systems for some time now do not use timers and regular wakeup periods if that's what you are talking about. this is called tickless.

[@INeedAttentionEXE]

So that's what HDC means when I want to get a window

[@MrEnsiferum77]

0:52 Garbage collector visualized

[@tobortine]

STM 14,12,12(13) Anyone?

[@MorningStarChrist]

Goron

[@pvc988]

r16 and r17 ;)

[@chickenjason123]

Press F for Intel

[@dosomething3]

“Context switching“ is just shorthand for “CPU context switching“.

[@Originalimoc]

Please enable your auto-sub(English)!!!

[@zes3813]

wrg

[@bonniedean9495]

kjd

[@lalalalexie]

yeah but the illusion IS TERRIBLE

[@BoPplle]

사탕 맛있어보인다

[@Aemilindore]

WhatsApp, what is it? its not secure. Thanks for reading.

[@adaptare]

Fiiiirst. Finally.

[@Metinator1]

nah you are third only

[@iminni3459]

nope

[@adaptare]

Damn haha

[@Chriva]

I've fallen for it a few times too lol. Congrats for being one of the first people anyhow :P

[@dannynewman82]

First

[@semibiotic]

Boring. Don't ever try to tell all things at once. That's silly. In order to underdtand details of context switching, you need first to clearly understand how CPU works (regs, memory, stack), how it handles IRQ, how interrupt handler must preserve program state (unless CPU makes that for it) ... And only after that, one could actually understand how interrupt handler or syscall could switch between proceses (and how that's made in different CPUs). There is no any sense to do that you do. People who doesn't have required knowlege just wouldn't remember anything, others - would be annoyed to listen looong and crumpled explanations of elementary things (intead of get to know something new). That's time waste.

[@UltrMarine]

15 minutes are too long for a video.. You can easily explain cx in 4-5 minutes.

[@danielgeci4513]

nobody cares what a guy using 2 imacs has to say