Razavi Electronics 1, Lec 36, Common-Source Stage II

[@rubenghazaryan6093]

Mr. Razavi your smile in the end of each video is just great.

[@shanmukhadasari8650]

@vlsi_analog1

[@zjwang573]

mysterious

[@StaliN_29]

[@bassamsleiman-i5q]

it really motivates me

[@tinius7mosvold807]

Was scared for my analogue circuits exam before I found this playlist, the Razavi god has answered my prayers

[@amrabdelhamid3778]

Best Gift you provided to Electrical Engineers! Keep the good work up, Thanks sir!

[@wagsman9999]

Each one of these is like unwrapping a great gift. Thanks again!

[@shadyyoussef7727]

Nice lecture ❤❤ , We are grateful to you Prof. Razavi

[@victrixmortalis7823]

38:29 1 minute silence by Razavi sir for Gain Coming out to be so low according to our choice parameters literally sir is Great!!!

[@__Blank___]

great, learned a lot from you than i studied in book.

[@hashimabdelaziz9941]

حبيبي يا عم رزافي ❤

[@ashishnorris4808]

37.50 sir i am a student watching this series in 2024 march , is electronics saturated now ??

[@aparnanagarajan7723]

great videos...thanks a lot , Master of electronics __/\__

[@sahhaf1234]

@35:00 so what is the conclusion? it seems the gain is stuck at 2 and cannot be increased.

[@NamHoang-ve7yj]

So the next part, we replace the Rd by the ideally current and continue to find the way to increase the gain.

[@animeshdas6866]

All of this is really good but what about the r0 we looked at previously? EDIT: Never mind. That's a CLM special.

[@anandsreekumar6687]

At 35:00, Prof. says (W/L) can be increased by keeping Id constant (only downside being sub-threshold conduction). But we know Satn. Id = (1/2)*unCox(W/L)(Vgs-Vth)^2 => Id prop. to (W/L) => Vds still decreases. Is this also not a way to explain why (W/L) cannot be increased indefinitely ?

[@tanmoydutta5846]

Sir said, to some extent we can reduce V(gs) and this would keep Id constant more or less, since Vgs - VTh would reduce by factors of a square...

[@ManivannanS-u6u]

if we keep of reduce the Vgs then at one point it will be less then vth so the mosfet goes to off state (subthershold region) where id follows different formula

[@pankajdhingra9985]

If we connect a current source in place of Rd, then Id will be constant (considering large scale), any change in input voltage will not cause a change in output current because of current source....so how will Vds will change and how we will get the gain we require?

[@__Blank___]

you have to think more practically.

[@windee417]

We lose that current source in small signal model. :facepalm:

[@alexandrosanastasiou1964]

To test for any changes you go into Small Signal Model so you open circuit the current source. For large signal model, this does not happen so you practically don't see any difference. Where is the confusion ?

[@abhishekshankar1136]

@@windee417 thats not the question he is asking , he is asking - since current source will have a constant current , how will Vds change ? since the drop across the resistor (which is acting as a current source) now remains constant , how do we acquire the required gain?

[@vivekkeviv9506]

Any sources having constant value will be vanished off in the small-signal model! that's the idea!!!

[@chaitanyabalaga9830]

If it is a constant ideal current source then from Id vs Vds graph the value of Lambda=0, So r0 = infinite will make gain infinite but why this is not happening ?

[@mkrishna7682]

nice lecture sir , can we more videos on cmos structure sir

[@sahhaf1234]

But when the r_d is replaced by the constant current source, will the device still be in saturation? Also, must the current passing on the constant current source be the same with the current that arise from v_gs?

[@lastminutedash6997]

48:07 Since a dependent current source exists, shouldn't we find the total resistance similar to thevenin resistance? Doesn't this current source has an internal resistance/impedance?

[@許祐嘉-u1c]

You can write KVL around the loop of Rd and ro. Actually, Rd and ro share the same nodes(Drain and GND), so they are in parallel to each other.

[@yashiroisana2622]

thanks

[@mnada72]

Why in calculation of input impedance the output port is not shorted ? As is the case in calculation of output impedance

[@mnada72]

Answered at the next lecture kzbin.info/www/bejne/i5a7pax3aZd4orc

[@sharmaji5298]

as per my understanding input port is connected to a voltage source, output port is just a node where we will read the voltage. It is not a source. During input impedance calculation, all the sources except input source should be made zero, right? output is not a source hence not shorted.

[@prasantnair1590]

At 52:00 what should be the EXACT value of the current source? Equal to (0.5UnCox(Vgs-Vt)^2) or much greater? And how would we check the saturation equation in such situation?

[@shanmukhadasari8650]

@vlsi_analog1

[@gopalkrishna9130]

01:01:00 why the resistors are considered in series once and and parallel the next time ?

[@cywinewind]

Because the input side is shorted when we look at the output impedance.

[@chang-seopyuk3785]

42:30

[@shanmukhadasari8650]

@vlsi_analog1