Reason for Setup and hold time in flip flop | Setup and hold time | clock to q delay | FF using Mux

In this video tutorial, we are discussing the reason for setup and hold time in a flip flop. why setup and hold time required for a flip flop and what is actually that. We tried to analyze the internal structure of D FF and understand how Flip flop works, and why we need setup and hold time. We have discussed basically the following points.
0:00 Introduction
0:50 Setup and hold time definition
2:05 The internal structure of D flip flop
2:15 D flip flop using MUX
4:10 Mux using transmission gate
4:25 Transmission gate
7:20 D flip flop using transmission gate
10:22 Operation of d flip flop
12:30 Reason for the setup time requirement
15:00 Reason for the hold time requirement
25:20 Can hold time be zero or negative
28:30 Clock to q delay in flip flop
30:38 Summary
If you feel this video is relevant to your domain and useful, please like the video and subscribe to this channel.
Your queries/suggestions are most welcome in the comment section.
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#SetupAndHoldTime #LibrarySetupAndHoldTimeOfFlipFlop #ClockToQDelay

[@D-KAMALAKKANNANM]

I understood this concepts clearly only by you thank you sir

[@nghiahiepbuiphuoc8946]

Good instruction!!! I love your videos. I'm a layout engineer from Vietnam. I would appreciate if you add English subtitle in every video to help everyone understand easily. Thanks in advance!

[@TeamVLSI]

Thanks dear, I will try to add that.

[@durganaga9513]

Superb explanation sir. Now only got the topic clear 😊

[@TeamVLSI]

Thanks Durga. Keep supporting...

[@bharathhm2215]

Hi.. this video is one of the best explanations on the Setup & Hold topic. Thanks! So I have a doubt - For any flip flop will the Clk to Q delay be the same as the Hold time because both have a Tg delay + Inverter delay?

[@harisharyan5174]

Very good presentation and presentation... Looking forward for much more videos

[@TeamVLSI]

Thank you so much Harish🙂 Keep supporting.

[@nitiningle1991]

Excellent Job. Your channel will grow with time.

[@TeamVLSI]

Thanks a lot Nitin for your well wishes. Keep supporting!

[@shivaprasad7703]

Thank you so much for your effort...

[@rakeshbabu6291]

Really a great vedio... But I couldn't not understand the Negative delay. Could you please explain with circuit diagram. What's are the problem we will get with this negative delay? Actually if Tg=5 and propagation dalay is 6, Tg gate is ON output also captured properly then what's the problem with this Negative delay ?

[@TeamVLSI]

Hi Rakesh, I have discussed about negative hold time not the negative delay. Kindly try to understand this again.

[@prashantsaxena2477]

Excellent video. I had a doubt that in some other videos, people say that hold time is the delay of mux2 in the D flip flop. But in this video you say its the Off time of the Tg1 transmission gate. Kindly please clarify my doubt?

[@TeamVLSI]

Hi Prashant, Good point you have raised. I would say that mux2 dealy is clk-q delay. Anyway I would like to see the explanation where it is told that and request you please send me the link.

[@padmajmanore8886]

ultimate!!!!

[@TeamVLSI]

Thanks Padmaj.

[@Anjay17680]

Thanks for such great videos.. sir, actually i m in your whatsapp group where someone asked that why hold uncertainty is less than setup uncertainty, then u said that u watch this vdo u can find the ans..but sorry i am not able to get that ans here too...please tell the time point in this vdo which present ans for that question... thanks

[@TeamVLSI]

Thanks dear for reverting on this point, I realize, I have referred a different video. Actual answer of your question is at 9:28 on this video kzbin.info/www/bejne/fXm3pYGkfcyVo7M If you can paste this thing in grp, I would like to reply there too so maximum people can get right answer. Thanks.

[@jahnavi6193]

Thank you for sharing your knowledge. Very very helpfull. I have a doubt. At 3:59 for clock "1", you say that Q is D, but if Qm is previous state, how Q can be D.

[@TeamVLSI]

Hi Pooja, Thanks for your kind words, Now coming to your doubt, Qm is nothing but D only.

[@jahnavi6193]

@@TeamVLSI ok got it. Thank you.

[@krishnanerella2742]

Sir this explanation Is so good😍😍.. Plz do one video on low power technics like level shifters, isolation cells,..

[@TeamVLSI]

Thanks a lot Krishna. Keep supporting. We will do the sessions on said topics.

[@praneethd.shetty3197]

Best explanation sir... thank you 😊😊

[@TeamVLSI]

Most welcome Shetty.

[@kshitijgurjar7499]

very beautiful expln...pls more videos on these STA topics.

[@TeamVLSI]

Sure, Kshitij, Very soon.

[@prashantsaxena2477]

I had a request that can you make a video on Hold time analysis with multiple clocks . For example, what will be the hold time equation between a positively edge triggered launch flop and a negatively edge triggered capture flop. (both launch and capture flops having different clocks). Or is there a video already on it?

[@TeamVLSI]

Sure Prashant, We will cover that on upcoming video.

[@ramsaivelidandi6777]

good explanation sir ....can u explain about skew groups in detail?? it will be helpful ......

[@TeamVLSI]

Sure, Will try

[@pavan.kumar.muttinenimutti9977]

thanks for giving an good information,please tell about half cycle path

[@TeamVLSI]

Welcome Pavan. I will try in future.

[@pavan.kumar.muttinenimutti9977]

Thank you

[@habibakhatunnesaragi6259]

Good explanation

[@TeamVLSI]

Thanks @Habiba

[@AyanDelagger]

Thank you so much

[@TeamVLSI]

You're most welcome Ayan. Keep supporting !!

[@jyh4820]

謝謝你的影片！

[@ganeshprasadbk1692]

Great video!! Your whatsapp group is full!! Instead you can have a telegram group since it can accommodate more people!!

[@TeamVLSI]

Thanks Ganesh, We have already a telegram group. You can find the link in description of video and join.

[@ganeshprasadbk1692]

@@TeamVLSI Thanks for the reply. I have joined the group already by searching in telegram. But for your info, the link provided is broken

[@b.asishdeepak5073]

sir I want to join in your whatsapp group but is showing members are full please add me

[@veeranjaneyulumoreboina1183]

Nice explanation

[@TeamVLSI]

Thank you, Keep watching.