Resolving a current control mystery in PWM converters

[@miguelsanz836]

Thank you very much for your videos, you can not image how welcomed they are. I am currently pursuing my PhD in power electronics and focused in WBD (you did excellent videos covering this topic). It would be great if you could treat some additional topics from Dr. Robert Erickson book as Canonical models or extra element theorems. In my opinion they are an excellent tools for understanding the exciting world of power electronics. Congratulations for your channel.

[@sambenyaakov]

Thanks and best of luck with your PhD research.

[@stefanoconti4426]

Outstandingly clarifying explanation, thank you very much!

[@sambenyaakov]

Thanks

[@justinn771]

Sir. I can't thank you enough. Hope you have a nice weekend.

[@sambenyaakov]

Thanks

[@trevthea5781]

Awesome videos. This knowledge is timeless. Keep sharing please.

[@sambenyaakov]

Many thanks

[@thefekete]

I had to program a 2 kW 3 phase buck converter in PCCM and then again in ACCM, and don't have any academic background in the subject (luckily my colleagues did ;).. needless to say I learned quite a bit about power electronics in the process. But with that crash course, I'm at least able to follow your videos and find them extremely helpful for trying to fill the many holes in my knowledge of the subject.. thankyou so much! I always thought of it as the PWM affecting the derivative of the average current.. or I guess that if we increase the PWM, the rate of change of I_avg increases and that the controller was then balancing on that edge -- basically speeding up or slowing down the rate of change to maintain steady state.. but your explanation makes much more sense😉

[@sambenyaakov]

Thanks for sharing. Welcome to the club.

[@mbaniarit]

I really liked the way you setup the challenges. Can we explain the mechanism of the first one @6:01 without going into parasitic resistance? For example, how about this approach --- as we change Rl from high to low (equivalent to increasing load current), the output capacitor starts discharging faster, which means Vo can no longer be same as DVin. As, Vo goes down, [Vin (constant) - Vo] is higher, increasing the current in the inductor. I believe, this is what we will observe even in Spice if we do not model the parasitic resistance, but just do a step change in load resistance. What essentially I am telling is that the expression Vo = DVin is not true in transient and we have to follow the differential equations, considering the capacitor voltage as a state variable.

[@sambenyaakov]

Please see the supplement video I just published and then we can "talk".

[@mbaniarit]

@@sambenyaakov Sounds great...Thanks. Please keep challenging our thought process.

[@sambenyaakov]

👍

[@kolinevans9127]

Very helpful, what I’ve learned is it really is all in the details, thankfully I’ve been able to learn this Thanks for sharing

[@sambenyaakov]

Thanks for kind words.

[@LeChickensX]

Why do you need the series resistance of the inductor to show how the current changes? Isn't the average current through the inductor given by periodic steady state analysis? For a buck converter, it is given as: = /RL where is the average current through the inductor, is the average output voltage, and RL is the load resistance. Therefore, changing RL changes the average current through the inductor.

[@sambenyaakov]

Yes. This is obvious. But what makes the current to increase and keep constant Vo. And what about AFPC in which there is no changing resistor but a storage capacitor ?

[@TotanDas1991]

prof. if you see a practical converter or a simulated one you can not justify your proposal because parasitic resistance is very small, a large current can only make such voltage difference. It's the inductor properties that make the voltage difference.

[@sambenyaakov]

Again. What inductor properties make the current shape sinusoidal in active power factor correction. Please explain.

[@TotanDas1991]

@@sambenyaakov for example in boost PFC the inductor is shorted to ground to increase current and then let go to reduce the current ( During SW off inductor build up voltage (inductive Kick) and boost the voltage each time ). If the load is high, to maintain output voltage inductor current has to be high enough(during SW on) to boost the required voltage which is controlled by the controller. Ldi/dt =V is the mathematical term for the inductive kick.

[@sambenyaakov]

Hi Totan. Thanks for not giving up😊I like the debate. Please see my upcoming video that I will post in an hour or so. WE can then talk if you still have doubts.

[@jorgemariofernandezfuentes3399]

I'm always watching your videos!! Greetings from colombia

[@sambenyaakov]

thanks

[@davidbourner9197]

Sam - I have set up a few very simple constant duty cycle simulations for buck converters and found that the incremental resistance you describe does not seem to apply in such a case. Clearly if there is no change in duty cycle and with only the load being changed in such a simulation, the current is clearly not set by incremental resistance. Maybe I have missed something.

[@sambenyaakov]

To see th change set up a closed loop for constant voltage and look at the duty cycle when chaging the load.

[@WalidIssa]

Sorry to be odd among these comments .. May be I am wrong ... I understand your point of how D and Vo are fixed while the current changes and you pointed to parasitic voltage drop ....but ... Why in simulaion where there is no parasitic and you have the same, fixed D, Vo and different Io. Have you looked at the energy stored in the core ? I think this contributes here ... in transients D changes to store more energy but setteles at the same D while the energy goes as current ... if you increased the load current more, the energy will no longer be enough .. or I missed something

[@sambenyaakov]

So in your opinion, what would make the current change direction a bidirectional buck boost?

[@WalidIssa]

@@sambenyaakov I see the same concept but in addition, in bidirectional buck boost, the controller changes the D in trasient then energy and also changes where it is applied, you have two transistors ... if the parasitic is the reason, we should have different results in ideal simulations. What do you think

[@sambenyaakov]

Hi Walid, thanks for not giving up😊Please see my upcoming supplementary video that I will post in an hour or so.We can then talk further if you still have doubts.

[@sambenyaakov]

@@WalidIssa Don't worry, I am not in the habit of embarrassing people. I do mention others only after getting their permission. Hold on the new video will be up soon.

[@sam7901]

Another nice video Sir. Maybe we could also think of it in the following way... If output voltage drops (For a buck for example), as would happen if load increases, (or there are parasitics), the only way for the controller to maintain a desired Vout would be to push more current to the output capacitor. This can only happen if dury cycle increases. In fact the state space averaged equations in CCM for a buck are in strict feedback form. Meaning rate of change of output voltage is dependent on inductor current (like a virtual control) and rate of change of inductor current is directly controlled by Duty cycle.

[@sambenyaakov]

Hi Srinath. Thanks for comment. You are correct but this is momentary as there is no DC current via the capacitor. See my upcoming supplementary video on the subject.

[@Dc_tech386]

Exactly books don’t hold all the right parameters I am trying to control the output current with out dropping the voltage but so far only the tl494 ic I noticed can turn down current and the voltage not drop I try the ka7005 but it’s not the same as may people believe

[@sambenyaakov]

Thanks for sharing

[@tsuriel3189]

thank you professor! very interesting, as usual :)

[@sambenyaakov]

👍

[@ezranoam]

Great video, thanks SBY! I think that in buck converter, not changing at all the duty would still result in correct enter into ccm when the load is increasing. The reason for that is the load will reduce the output voltage, which will cause Smaller slope, which result in a higher current at the end of the cycle. It would take a few cycles but they call him to will be stabled at ccm. Furthermore, if the parasitics are small enough the voltage will be almost constant for a verity of loads at ccm. WDYS? Do you agree or I missed something?

[@sambenyaakov]

Hi Noam. Thanks for discussion. I guess you consider an "ideal" case? No resistance. But this is cheating😊Half baked. In the pure ideal case the capacitance is infinitely large. What then?

[@ezranoam]

@@sambenyaakov yes that a good point.. I just measure a few weeks ago in the lab a forward converter with a constant duty cycle. The output voltage was about constant while it did enter deeper into ccm which suggest there is another mechanism as well. I was able to see that the current build during a few cycles while the output voltage slightly drop and rise back. I think it is due to the process I just described.

[@sambenyaakov]

@@ezranoam The main point that I was making is that that in Buck, for example, saying that Vo/vin=D is too simplistic. I guess you would agree to that?

[@ezranoam]

@@sambenyaakov definitely, I just want to add there is another mechanism that supports the ccm change.

[@sambenyaakov]

Noam, rephrasing what you are saying: when the average voltages on both side of an inductor are not equal the current will increase. Isn't that simply dI/dt=V/L?

[@RanjithSethu_findmehere]

Sir in a ideal simulation matlab or spice of a dc dc converter , there are no parasitics , so what is happening there ?

[@sambenyaakov]

There must be , at least an initial dD to get the current going on direction or another. My main purpose was to point out that in a real system, with parasitics, D will be somewhat different in the two directions

[@perrybakalos7340]

very nice thought share once again, thanks!

[@sambenyaakov]

Thanks

[@krzysztofwrzaka8553]

What happened with Dr. Slobodan Ćuk's comments under this video ? Did you banned him from commenting on your channel ?

[@sambenyaakov]

Sorry, I had to rmove his comments from this channel. I just cannot carry out with him a discussion in a civilized manner.

[@electronic7979]

👍

[@sambenyaakov]

😊

[@سعيدحواصلي]

شكرا

[@sambenyaakov]

Thanks شكرا

[@atahghighi]

Wrong , not correct, it doesn't have anything to do with parasitic resistance. Very simple all the converter you mentioned are voltage mode they deliver constant voltage no matter how much current the load are drawing

[@sambenyaakov]

So how come the current goes one way in Buck and the other way in Boost while the circuit is the same and the transistors are switched the same? Can you explain this? Watch the video again.

[@atahghighi]

@@sambenyaakov do the transfer function for the input impedance of a boost converter,