review of 'Porting from Wishbone bus to Avalon bus in SoC Design' - Koba Kiria (voice issues)

[@bennguyen1313]

My SoC's Arm-M3 is an APB3 master.. so how how would you convert a Slave wishbone-bus device to an AMBA 3 APB or AMBA 2 APB slave? (i.e. port a Wishbone slave to APB3 /APB2 slave). For example, in Libero, you can import/check an HDL file, and in the design-hierarchy tab, you can right-click 'Create Core from HDL' and have the tool *attempt* to map the top-level signals into a APB bus (slave role / Library AMBA2). However, it's not perfect, so would like to do it manually!