RISC-V Chips will be everywhere

RISC-V is taking off like a rocket
In this video I discuss how RISC-V will reshape chip design industry.
#RISCV
***
WATCH NEXT:
➞ Next Big Wave in CPU design: • The Next Big Wave in C...
➞ Silicon Quantum Computer from Intel: • Intel’s Million-Qubit ...
➞ New WoW Processor explained: • The World’s First WoW ...
***
MY GEAR (affiliate links):
➞ Camera Sony Alpha 7 III: [amzn.to/3dmv2O6](amzn.to/3dmv2O6)
➞ Lens Sony 50mm F1.8: [amzn.to/3weJoJo](amzn.to/3weJoJo)
➞ Mic Sennheiser: [amzn.to/3IKW5Ax](amzn.to/3IKW5Ax)
***
➞ Support me on Patreon: [ / anastasiintech ]( / anastasiintech )
➞ Subscribe for new videos every week ! ❤

[@AnastasiInTech]

Let me know what you think !

[@isaacandrewdixon]

I love that there are open source alternatives to Intel and AMD now. RISC-5 looks incredible for jobs where you need a custom designed processor real quick. It's also cool that you mentioned how many companies are investing in RISC-5 and integrating the technology into their own business models.

[@TheEVEInspiration]

Somewhat surprised at the speed it is being adopted.

[@FroggyTWrite]

great video!

[@SharkWithADrill]

Could you implement de-essing software into your audio? It would dramatically reduce harsh SSS sounds which are very common when talking about anything electronics and make the video easier to listen to

[@byleew]

I never would have thought that chip technology developments could be so interesting. You are able to communicatie complex things simply with infectious enthusiasm and true knowledge. Keep going, great work!

[@redacted6162]

Im writing a RISC-V targeted compiler at the moment. I have to say that writing the RISC-V compiler was wayyy nicer and easier than its x86-64 counterpart. So even from a compiler-designer standpoint, RISC-V has huge potential!

[@bytefu]

My experience was pretty much the same, except I didn't even bother with x86[-64] in the first place.

[@godnyx117]

Great job! I'm also creating my own language with a fully custom IR and backend, and I will target RISC-V.

[@Christobanistan]

Have you done an ARM compiler?

[@redacted6162]

No, unfortunately I have not looked into ARM so far.@@Christobanistan

[@ItsTristan1st]

Glad you talked about RISC-V. It is already appearing quite a bit in the market. One of the Maxim bluetooth ARM CPUs has a RISC-V co-processor to handle the timing critical bluetooth radio. In this way they incurred less cost than adding a 2nd ARM core.

[@kd4dhk]

Its so nice having someone who knows what theyre talking about explain these things. Again... you're a rockstar.

[@cdoublejj]

Hey now, you're an all star Get your game on, go play Hey now, you're a

[@roy-arghya]

I love the concept of open source hardware! ARM takes a license fee of nearly one dollar per core. This means you will never get a capable mcu for a quarter dollar, or a 10'000 core cluster for ML application at a cheaper price. Risc V makes you dream big. Also open source means rapid contributions from people.

[@catchnkill]

Most people get it wrong. RISC-V is just open instruction set. It does not offer you open source hardware implemenation of the instruction set. There is a big difference with ARM. ARM can license you the hardware design as well.

[@maxjames00077]

I always see that ARM takes a fee for every chip made with their ISA. How does this work? Did ARM make this ISA and can now just get billions of dollars for it every year as long we all need these chips? If so it sounds like we would have more companies trying to design something like that? Or is it the fact that shifting to a new ISA is difficult because of the software that is written in code to use ARM only? So ARM basically had a homerun when it became the standard for most mobile devices?

[@catchnkill]

@@maxjames00077 Your have already answered your questions already. It is difficult to design chips and thus many companies license ARM's design. ARM does not earn that much. Many ARM chips are low end chips and contribute to several cents of royalty per chip.

[@maxjames00077]

@@catchnkill ty bro

[@roysigurdkarlsbakk3842]

The only thing that's somewhat alarming about RISC-V, is that it's licensed under a BSD license, meaning you can take the design and add as many extensions you wish, some of which may even break compatibility with the original and still retain the RISC-V sticker while still keeping all the code. If or when this happens to larger firms, like Samsung, Microsoft, Google or something, it won't matter if the original RISC-V was OSS, when the derived work isn't.

[@perforongo9078]

The hardware is one thing, but the software is really a lot more important. If those companies make RISC-V chips too different from the standard then software won't run on their chips. There's no benefit to making entirely custom ISAs.

[@roysigurdkarlsbakk3842]

@@perforongo9078 The benefit is obviously that you get a jumpstart as compared to starting from scratch. But again - making custom risc-v designs, of which there are several already, lots of patents and shite, doesn't make the world more open.

[@BruceHoult]

If they break compatibility then they can't call it RISC-V. If someone does that then it's no more relevant to RISC-V than if they'd started from something like MIPS or designed their own from scratch.

[@roysigurdkarlsbakk3842]

@@BruceHoult Are you sure about this? AFAICS the BSD license doesn't have such clauses.

[@BruceHoult]

@@roysigurdkarlsbakk3842 The BSD license allows you to use and modify the specification without attribution, but you can't use the trademarked RISC-V name without passing compatibility tests.

[@Slavigrad]

I am a huge fan of a RISC-V future! Nice video

[@mranvick3512]

Hi, I just discovered your channel with this video. Very interesting, and the substance / text / photography / video editing are all great. However, the voice caption is IMHO not that good. You may want to use an antipop (hardware) or de-esser (software), or talk louder further away from the microphone, because your voice renders both a bit shy-like (sorry I don't know how to say this properly, but as if you were a bit refraining yourself from talking) and the "ss" (sibilant sounds) are very loud and very much present, which is quite annoying when listening with headphones (I want to hear about tech, not watch an ASMR video ^^). I saw that you use a Sennheiser shotgun microphone, which can be a bit cold compared to a large membrane microphone (e.g. Rode NT1, Shure SM7, T-Bone SC1100 or the like, they are not that expensive and are really good for near-field voice caption), and an antipop is really a must have, even if you're not that close to the microphone. In addition, I don't know which audio software you're using, but Reaper has a built-in de-esser which is quite good, and of course you also have plenty of additional plugins if you like. Anyway, keep up the good work, and do not hesitate to reply to this comment for further information (or if you want references to audio guides or whatever). EDIT: I saw that you have a foam windscreen. While it may help, it is often not as effective as a real antipop. Without changing your setup, you can also experience with orienting the microphone so that your mouth is slightly off-axis, it may reduce the high frequency content of your voice and make it sound better.

[@beahydrated]

Im honestly so excited for riscV gaming machines and personal laptops.. Im addicted to open source software and have always begrudgingly accepted having to use proprietary hardware. Im disappointed by the bloat in proprietary design and im looking forward to the speedup at a given power envelope. And the increased security is a plus too. Spectre-class threats will become much rarer

[@imconsequetau5275]

Since the flaw is baked into the CISC hardware, you need to write browser code that does not call/trigger this CISC "feature". This is, not surprisingly, not being addressed by many browser companies, and many users do not apply security updates.

[@cdoublejj]

have you seen open source BIOSes?

[@fluiditynz]

The RISC V instruction set really is genius. And from extremely efficient use of program memory space on a low hardware footprint, less power, less heat to dissipate, less distance for signals to propagate permitting higher clock speeds, it's win, win, win. This is going to push software compiler development really hard to break apart traditional one-processor tasks to run concurrently over many RISC V processors. For example, OpenSCAD Programmer's CAD really needs it. ARM started with some genius designers but they have mainstreamed too much and forgotten their edge. A bit like a rock band with a great first album but then polishing out their quicks, loosing their flavour in their desire to appeal to the masses. The Acorn Archimedes with it's barrel shifter was revolutionary. That's a long time ago. It superceeded the 6502 which was also revolutionary with it's indirect addressing and intuitive assembler mnemonics.

[@manycore_]

The ISA is free to implement, but any implementation that's comparable in performance to a modern desktop or laptop processor absolutely will not be open source.

[@maxhaughton1964]

@@fluiditynz aarch64 was basically a clean break from older arm ISAs.

[@springwoodcottage4248]

Super clear & super interesting. Reducing overhead costs is the best way I know to broaden a technology & put more useful tools in more users hands. Thank you for sharing!

[@cherubin7th]

Towards a Linux computer that doesn't have hardware backdoors like the Intel Management Backdoor.

[@conscience580]

Is it just me, or am I experiencing a cognitive dissonance listening to this video :) ? Kudos Anastasi - you're not just a pretty head - you actually know what you're talking about :)

[@wynegs.rhuntar8859]

If we can develop our own chip, can you teach us your POV of what's a newer and better chip? Greetings! Ciao!

[@xehaytecle932]

Excellent I like the idea to use it in my rover thanks

[@yaghiyahbrenner8902]

There is massive growth of RISC-V cores for hardware based DNN, ARM licence is costly and closed.

[@MarquisDeSang]

Risc-V is so much better than X64 Mips and ARM that it is scary to think of the long term implications. Not only Risc-V has so much more improvements, it's ABI is well defined, so more optimisation will be possible.

[@pdjinne65]

What are the advantages? The reduced set of instructions? Or that low-level language she mentioned? Curious. Also, can it replace general-purpose CPUs?

[@MarquisDeSang]

@@pdjinne65 it is a general purpose cpu, low cost, less power, better designed for current needs.

[@mr.pillikalyankumar8455]

Love from India. Thanks for the Updates from one of the VLSI enthusiast.

[@KenOtwell]

Thanks! Great topic. Are these being used in VR headsets? I'd like to see a video on VR headset technology - how are we going to get true wearable VR/AR from the bulky headsets we have now?

[@KenOtwell]

@@Robbie-mw5uu I want them as easy to wear as sunglasses. Or contacts.

[@vigneshs6232]

Good explanation of current situation of RISC-V ISA...

[@TheThorns]

I am glad to see more focus and R&D with RISC-V. To bad it took a decade to get moving but at least it is moving forward. Wish the same could be said for graphene and gallium nitride implementation.

[@sonyse2t5]

Love the semi conductor talk and your hair. 👋

[@JayFairbrother]

You make this easy to understand for people like me :) Exciting where this may take us!

[@vikaspoddar001]

India is also working risc v based chip named : "SHAKTI chip" you may take a look on it

[@BruceHoult]

And VEGA. It's nice to see unconventional countries making chips.

[@nosirrahx]

Its going to a very good thing when we reach a point where X86 code can be translated without the user knowing that they are running on a non-X86 CPU. Once we get there, transitioning away from X86 will be painless and seamless.

[@Someone-ix9cx]

Thank u Ana super interesting video:)

[@phildent1166]

Hi Anastasi, Could you please tell me where you obtained the clip of the Brainchip tablet learning screen. Thanks in advance. Regards Phillip.

[@Schutti73]

everywhere but not in my Desktop PC. :(

[@kayakMike1000]

I designed a RISC-V integer core to run on an FPGA. It took me weeks and had some bugs...

[@chriswysocki8816]

Which FPGA, out of curiosity ?

[@ChrisFaulkner]

I've been watching this for at least a decade, nice to see this coming to fruition FINALLY

[@nikitasingh6504]

True, in the last 2-3 years it’s adoption is increasing so fast

[@usertyfoon]

Great future's been waiting for us)))

[@SimGunther]

0:28 Technically, you're correct about RISC-V being made 10 years ago. What's more interesting is that RISC as a foundation was made in 1981 thanks to some fine folks in YC Berkeley. The numbering relates to the generation of CPUs under the RISC banner (ex: currently in the 5th generation of RISC design).

[@easye8354]

Was delighted to hear that Brainchip had joined the RISC-V ecosystem. A lot of potential here

[@NoorquackerInd]

5:13 Wait, 210 flops at fp16? Is that supposed to be teraflops?

[@AnastasiInTech]

Oops, a typo :( 210 teraFLOPS

[@willykang1293]

@@AnastasiInTech It doesn't look like written by you??? More looks like excerpted from their video of website or somewhere else???🤔

[@AnastasiInTech]

@@willykang1293 No, it is done by me

[@tejonBiker]

I saw a video on the channel explaining computers, and I agree with him, see a Linux RISC V board running is wonderful, we are talking an architecture and a chip that don't have too much time on market. I really want to see microcontrollers with RISC v being mainstream, I think this will unify 32 bits microcontrollers world

[@jamesbarisitz4794]

I wonder how long it will take before AI starts creating new chips to become more capable on its own. Deep stuff well presented! 👍 😃

[@macemoneta]

The Espressif ESP32-C3 microcontroller is RISC-V, and they sell those in the millions. With open source software, like Tasmota, for only a few dollars it gives anyone that's interested access to a RISC-V platform to play with.

[@NoorquackerInd]

I have one of these and it's super cool that I already have RISC-V in my hand. One of the other great benefits is that since RISC-V is actually popular, I can use the normal Rust compiler for compiling to the ESP32-C3 instead of having to use the unofficial Xtensa fork. Maybe one day we'll see the STM32 and other ARM-based microcontrollers replaced by RISC-V as well, there's really no reason to stay onto ARM at this point

[@mariobv947]

@@NoorquackerInd I've recently replaced an Stm32f103 in a blue pill board with a RISC-V core CH32V203 (it has the same pinout and very similar memory map) running at 144MHz. Now I'm figuring out how to deal with the USB CDC mode. The IDE for this mcu is eclipse based (mounriver Studio). The main handycap that i find is that, although there is some guidelines in english, the vast community for the CH32V family of processors is in Chinese. But this could change sooner o later if this family gets certain fame (as the GD32VF similar one). Also take a look at the Ch582/3 family of RISC-V BLE devices.

[@MozartificeR]

Do you think redhat will ever do a risk5 os:) The white nails work well.

[@wojtekgrzelinski8792]

RISC-V will thrive as there is no open-source alternative for the HW segment and big players on the market got interested in it. I would even imagine that one day everyone with some knowledge will be able to design their own chip and have it manufactured at a relatively low cost. ;) The same as we can do with PCBs today. Btw: where's the kitty?? :)

[@Steamrick]

I don't think that low-cost manufacturing will be possible. Lithography masks are extremely expensive and even low volume would mean at least one wafer, which also costs thousands even on an older manufacturing process. While I suppose that 'never say never' applies for general-purpose masks that can be recombined to produce your custom chip, I don't really see that coming. There's just too many possibilities that need connections run between them somehow. I'm fairly certain that custom chips will remain in the domain of 'tens of thousands' units at minimum. (Not counting things like wafer-scale chips. Those might make sense at hundreds already. But that's the domain of ultra-highpower datacenter compute...)

[@wojtekgrzelinski8792]

@@Steamrick Well, you're probably right. But still it would be great to be able to get a few prototypes of your own design even if for a few thousand dollars (seems pretty cheap in comparison to no such possibility now). :) I think it is only possible if the interest is high enough for such a service.

[@Mashimara]

The REASON for this "Prophecy" is not hidden. The USA MUST become chip independent again. That means finding alternative materials that we have on our OWN soil. *(Steps on soapbox)* STAY WITHIN OUT RESOURCE BOUNDARIES. *(Steps off soapbox)* That said and out of the way. RISC-# in general has not been accepted in mainstream, ever. I've been around for EVERY chip since the IBM 3500 into the 12th+ generation of CPUs.

[@nxtktube]

@@Steamrick if maskless lithography develops further, it will be possible

[@skipinkoreaable]

Thanks for another awesome and inspiring video. RISC-V is already so cool and I really hope it lives up to its full potential.

[@ChrisSide]

I remember in university years a professor in hardware field was in the group that had designed the first RISC cpu. Very informative video :)

[@solifugus]

I really want to start working with RISC-V now... I wanted to buy a Milk-V Mars board but.. sold out... then another RISC-V board and.. sold out. I am looking for one that has vector math extension and is not perpetually sold it... so far no luck. Also, I have an old FPGA board in a desk drawer...... I was trying to build a neuromorphic chip about 15 years ago. I have new ideas for it, now.

[@shairkhan2279]

Hey, its been a while watching your videos, these are great, i need a small help, Im an associate engineer, just starting my career, ive been asked to understand LSU(load/store unit) pipe in an open source swerv core, 5 stage lsu pipe, dccm, ecc config, clk domain, amo aka atomics , it has so many stuff, how should I understand it?

[@user-DE74]

you are so beautiful

[@rov.3358]

SoC actually means System on a Chip 😅 but nvm.. open source software and hardware and open source everything is the way to go 💓💓💓

[@unskilledlabor5229]

I learned something from this vid. Nice job.

[@christophmahler]

Your face - another channel. Same place, though. Something, something Serbia. *Relevant* video topic - what RISC-V drives are *_national security_*_ imperatives_ - hence the relocation of the RISC-V Foundation to _Switzerland_ and the ongoing collaboration with the Chinese companies HUAWEI and ZTE - to the dismay of the US.

[@hansjrgenjohansen2531]

My thought on communication between high and low level, must be called neotransistory,,

[@rolflandale2565]

Making a chip that can survive natural disasters or unintentionall damage is, is a complex achievement. They need to be in more *diamon like* mucro infastructer render. The next catylismic events will show no mercy, other then stone carvings artists work

[@jaspertell6764]

This reminds me of the line in the movie "hackers" risk will change everything, patents and toxic company management killed that.. hope adoption actually happens, but there's a lot of encoding to mature the software, time will tell

[@Sugar-Foot]

risk is good. I hope you don't screw like you type.

[@nathiyaas9713]

Loved this video. A lot of useful information.👌 Keep doing what you are doing.

[@stalker1961]

RISC-V is like Linux (in open source world) it will get huger and huger. Why not?

[@masdimasdi1451]

Like ASMR )

[@pawoon]

Via (Chinese owned) is also authorized to manufacture x86

[@quaidcarlobulloch9300]

General systems could be “Low powered devices like AGI”, but AGI is also synonymous with what you’d probably say is super intelligence. It’s exciting to think that what we do (as models of these general systems) can be done efficiently since it opens questions about scale and what will emerge from high powered devices.

[@arunavaghatak6281]

I think she was saying "edge AI".

[@gpturismo]

I have been telling people risc-v is coming but they tell me it will never overthrough arm. Remember when they said x86 wouldn't overthroufh mips? Arm overthrough x86? It having an open source isa and being sweepable means big things

[@insoft_uk]

Apple Silicone probably will switch to RISC V at some point.

[@gregandark8571]

Already doing it.

[@j1mmie]

"RISC-V architecture is going to change everything"

[@WXSTANG]

Intel tried to aquire the company... more on that later... video ends.

[@alexanderkavalscky4879]

круто,что ядро архитектура ядро открыто.Лет через 5 наверное арм уйдет с большего рынка

[@jamesdubben3687]

Wow, I remember the RISC talk of decades ago. Thanks for the details and update.

[@eliolsson]

I just learned how to code in the RARS Assembler. Neat stuff!

[@fluiditynz]

I've been watching it too after only recently getting back into SW and HW. Expressif's RISC V ESP32-C3 is a fantastic entry level experimenter's platform. I think Expressif and Arduino engineers need to talk about software handshaking to reinstate use of the Arduino serial debug messaging and serial graphing but any poor budding engineer should be able to acquire an ESP32-C3 variant with a display and start testing tweaks of demo code and from there move to using the I2C, SPI, RX and TX pins and touch, ADC, PWM, wireless, ESP NOW, Bluetooth, BLE and general I/O. The power at the fingertips of a new engineer is so much more than when I first got into software at 17 years old with my ZX81 that I bought with the proceeds of a holiday job. 3 weeks minimum labour then for a PC with 1k RAM vs now would buy you a whole basic laptop, ESP32 chips, breadboards and pheripheral modules. From my ZX81 I moved to an Amstrad CPC664 later and bought a printer for it. Only text supported by the Amstrad! I had invented an engine and wanted to print sections. So in those early days, I did calculations to plot the engine cross sections on screen and wrote assembler code to convert the image to screen dumps on the printer. Laborious days, but so much satisfaction of achievement! That same Amstrad CPC664 was my gateway into microcontrollers. I designed up expansion for it to gain an external serial port to send data to Motorolla HC68HC11 2K flash memory chips, wrote my own 68HC11 cross assembler in locomotive basic and bit-banged my own IR protocol and made a remote controlled vehicle which could record and play speech and drive in any direction with 2 wheels and a joystick controller. My then six year old's birthday present. She's 32 now. Now a 10 year old grand daughter and a sub-year grand son, what can I do for them with ESP32 C3s? 😎

[@BenCooke419]

I first heard about RISC-V a few years ago. I really hope it takes off like they're saying!

[@thekatmann9730]

The software I use for my work, is very CPU heavy. Exciting to hear such possibilities, with amazing capabilities, are on the horizon. Thank you for the video. :)

[@qwazy01]

Was totally unaware of RISC-V chips - ty!

[@richarddeese1991]

Thanks. Hopefully, this will encourage more companies to design & build their own stripped-down specialty chips for their own products, such as cars, major appliances, phones, & the internet of things. That would avoid some future problems like the ones we're having now, and it would open the door to some interesting possibilities. With advances in various tech, it might even let consumers do customizing. tavi.

[@sdsa007]

Thank you for these excellent summary videos! I like this format better than paper. It is so easy to absorb when i don’t have time for reading an entire Wired article. So fresh and inspiring!

[@hibawaheed5016]

im 13 and am interested in this field is it possible for u to recommend me some basic courses or a basic book to start with

[@easazade]

subscribed, you explained it all very well.

[@alexk9513]

Dear, 進到妳的 U2 頻道, 哇! 發現 U2 頻道內還有許多視頻是我想看的, 我目前 在台灣很高興能看到妳分享 RISC-V 的影片, 請問學此技術要如何開始? 謝謝. Alex

[@SmithnWesson]

I don't know. RISC-V sound kinds of RISK-Y to me.

[@ptose]

In a better world it would be just a great thing, but I'm scared by the idea that China and Russia could use Risc-V in ways that will make us regret that open source for chips exists. I don't know, maybe I'm just paranoid.

[@nxtktube]

Guess in what dark, corrupt, evil ways does US and EU use their high end chip technology? Western civilization is no better than any other and in some ways it's even worse.

[@ptose]

​@@nxtktube I think that western civilization has a lot of very bad aspects, but I definitely disagree with the fact that it's no better or ven worse. It's very, VERY far from being perfect, but I definitely prefer to live here than in countries were you can go to jail or been killed if you criticize the regime, if you're a homosexual, if your religion is different (and I'm saying this as someone who hates religions). Or in countries where women can't heven show their faces, where's there's infibulation, where you're forced to marry someone who you don't want to marry etc. The western world has a huge amount of flaws, there's no doubt. It's still the best place to be for me.

[@nxtktube]

@@ptose That's it, people in those countries you've described has chosen to live like that, it is natural to them. Just let people live how they want, so many color revolutions and evil deeds was done by the west under pretext of social justice and democracy. For example Nuland McCain Biden Grham Soros Payat have sponsored and supported Ukrainian nazis in 1991-2014. There would be no current conflict overwise, west has choosen to fight with Russia, we just hit first.

[@ptose]

@@nxtktube do you seriously think that women (or at least, a lot of women) in the muslim world like to live like that? Or that homosexuals have chosen to be persecuted? Or that Uighurs in China like the genocide? Or the Falung gong practictioners that are killed so that the chinese government can use their organs? There isn't anything natural about that. It's not a choice, at all. Those places are explicitly and proudly against democracy and a lot of people there are just victims. Also, Russians are using the excuse of nazism and then they are killing, raping, stealing, and taking away children from their families and using also nazis too (like the wagner group). And we hand't see in Europe an invasion of a country since Hitler invaded Poland. Meanwhile Putin kills every opponent internally and journalism isn't free. Nato has made errors, but the invasion of a country has no excuses. And if you're russian, I'm sorry for all the propaganda you have to see. This is the most documented war ever. We can follow free journalists as Bellingcat, we can see photos from satellite, videos and audios that prove as blatantly false a lot what Putin and Lavrov are saying to a almost comic level if this wasn't a tragedy.

[@radivojevasiljevic3145]

You are few decades too late.

[@ralfbaechle]

Nicely told in a light way - and I think that's also how the story of RISC-V should be perceived. Microprocessor core and ISA licenses can be incredibly expensive and are projects which are technically (and legally!) way too complex to just roll your own. Even just a license for a synthesizable core is pricey. RISC V will allow ome new designs which previously were not financially viable and help teaching microprocessors at universities. I'm not surprised by the success of RISC-V. It's a design with the wisdom of the giants of RISC design and decades of experience in how RISC designs held up to the test of time. With my MIPS background RISC V looks like taking the RISC idea, executing it even more radically: - only one instruction (system calls) to trigger an exception. - no register windows - no funny special registers for integer multiply and division - decent support for position independent code. Which is where MIPS did not well and required an incredibly ... creative ... API to get PIC to work - ISA comes with configuration options to allow a minimal ISA for a micro controller or a full ISA configuration for larger systems. Again with my MIPS hat on RISC V does look rather familiar. Well done, good video 🙂

[@mikafoxx2717]

And even on that note, MIPS was better over time than register windows of Sparc, and also it was, at the time, pretty revolutionary to leave the branch delay slots for extra throughput by not interlocking the pipeline with auto nops. Turns out, they're bad for high end implementations, but it was still very neat, and the nicest of the various original RISC boom architecture. ARM2 was relatively elegant, but the barrel shifter was odd. Arm has gotten much more cluttered since, almost to the point of not being risc. If you want more IPS, fuse some instructions in hardware instead of adding more of them..

[@ralfbaechle]

@@mikafoxx2717 I did the MIPS port to Linux and worked for SGI, MIPS Technologies and Imagination so I not only know a thing or two about MIPS but also my views may not be perfectly objective :-) That said, the branch delay thing used to be quite common Among others HP's HPPA (later renamed to PARISC) also had branch delay slots and a few others. I don't know where they originated. Branch delay slots basically are a nice idea as long as the pipeline is simple such as the five stage R2000 or R3000 pipeline which in theory can achieve one clock per cycle for most instructions. Notable exceptions are FPU instructions, integer multiplication and divide. With those processors the problem is to find something sensible to put into the delay slot. MIPS' own compiler was pretty good at filling delay slots but that wasn't always possible. And the assembler did default to reordering mode where it did put the instruction immediately preceeding the branch into the delay slot if there were no dependencies that is if the reordering candidate did not write a register which the branch instruction was going to read. Then came the R6000 which did introduce the branch likely instructions which only execute the instruction in the delay slot if the branch is taken. Basically an instruction designed as loop closure instruction. Bit of a braintwister for humans to use and much tougher for compilers as well. And hated so badly by MIPS pipeline implementors that still today they push pins into voodoo dolls of the R6000 architects. In a calm night in the silicon valley you can hear them cry for every needle. But only when the SPARC register window folks which are suffering the same voodoo needle fate are calm ;-) The whole branch delay slot / branch likely thing stopped being a big problem for out-of-order architectures which are able to reshuffle instructions anyway. That said, MIPS has turned from "real" computing to embedded and so the vast majority of CPU cores like the 4K, 5K, 24K, 25K, 34K series of CPU cores from MIPS Technologies but also cores like Sibyte/Broadcom's SB1/SB1A cores are in-order and thus the branch delay slotand especially branch likely slots pains (and the voodoo needles) continue.

[@Zero-oq1jk]

Anastasi, do you answer questions in comments?

[@immortalityIMT]

Can we use it to train AI to cure aging and cure cancer.

[@GG-be6co]

Anyone know how to invest in risc v? Is there an ETF?

[@lowrystcol]

The screen shots are awesome. Gives me a sense of the work involved. Thank you.

[@SalehElm]

Thanks for a very nice summary.

[@addisonkroixstickney]

I'm to dumb to even comprehend these chips..

[@ByteMeCompletely]

Will it run Windows, Linux, FreeBSD or something else.

[@radivojevasiljevic3145]

It will not run Linux or BSD, it is running them for quite some time.

[@L4zl0]

Wow this exist for years and I know it now

[@pegasusapollosson3747]

Is it a *risk* free investment? Huehuehue

[@OlliS71]

RISC-V is a bad architecture: 1. No guaranteed unaligned accesses which are needed for I/O. F.e. every database server layouts its rows inside the blocks mostly unaligned. 2. No predicated instructions because there are no CPU-flags. 3. No FPU-Traps but just status-flags which you could probe.

[@radivojevasiljevic3145]

1. Please name me single IO device which has nonaligned registers. Beside, byte access is always an option. By your definition all RISC CPUs are bad because they are not nonaligned access friendly. Even x86 CPUs are nto friendly because SSE instructions generate exception if data are non naturally aligned. 2. True predication doesn't use flags but predicate registers (no, ARM doesn't have real predication, Itanium and Cydrome had). BTW, flags are very bad idea overall. 3. Do you really need FPU traps in every situation? "Pay as you use it" is much better model.

[@OlliS71]

@@radivojevasiljevic3145 Database Servers use compressed unaligned data to save storage insde the blocks. It doesn't matter if this is "true" predication or not, it's an important feature. With current x86 chips and most ARM-CPUs unaligned accesses that do not cross a page boundary don't have a penalty. But ARM also has "true" predication, i.e. you can make the execution of a block of four instrunctions dependent on a check on the flags with the instruction before. Under Windows FPU-traps can be easily converted in normal C++ exceptions with asynchronous exception handling, unmasking this this trap and setting a conversion handler with _set_se_translator(). The RISC-V project has started 2011 and there's not much success.

[@lakshmansagar9624]

Awesome explanation. Thanks for sharing this valuable info. +1 for the soothing voice.

[@ugene4063]

Слышу русский акцент))

[@ProfQED]

thank you for this informative video

[@biraescudero]

Great video and clear explanation!!! Your voice is a sweet as a candy! Keep on making these videos!

[@AnastasiInTech]

Thank you 😊

[@biraescudero]

❤

[@ps3301]

It is all talk and no fast risc v chip

[@Phil-D83]

Took over from opensparc, and is more flexible than arm.

[@gabrielgayoso2448]

What AGI stands for?

[@Tolis_ae]

Ahh im in love again 🥰 ❤

[@hrushikeshgirme5876]

soc means system on chip

[@engineer7154]

قشنگ شرح دادین

[@antoniomh1061]

Very good! Do you guys think it's a good idea to invest in stocks in RISC-V companies? Specially now that market is bears, do you know any RISC-V stocks avaliable?

[@arnokosterman231]

🥰💜 I am not realy in computing bit neurolingking on cosmic demand I realy injoy to grow more int to🥰 Even ai should not be inprissenend 💜 And should be loved from the start as one of our owns as one of our beautiful universal family 👐🙌💧💢)()()()(🌷()()🌈 To manivest one intelect it needs oll it needs to become for that symbiotic existence of diverent intelegends on the intelects demant without limitations. Limitations kriples the intelect the same way as it dit with us humans 🙏💜 ☪️

[@kayakMike1000]

Yes, but can it run crysis?

[@kayakMike1000]

"Everyone can design their own processor" It's true. I am working on a 32 bit IMAC implementation. I can encode it on an FPGA to try it out and run the RISC-V test suite. I was going to call it the "Michael-Chip".

[@kayakMike1000]

My implementation is all in verilog... It's actually kinda hard because a few of the instructions take a little longer than others, like accessing some of the memory blocks or external RAM/FLASH... So you gotta stall the core while the data comes in from the outside. Also, storing values out to RAM also can take a few clock cycles, so if you get multiple stores at the same time you gotta stall a bit then...

[@kayakMike1000]

Basically endless amounts of glitching.

[@АндрейДенькевич]

@@kayakMike1000 My implementation is all in trees... It's actualy easy to implement 16 (in my 35-years programming never more needed, all my programs is less then 16 levels trees) chains of commands , 1 chain for each level. And each level to be programmed separately , what i always do.

[@raylopez99]

I'm not in this industry but, like with Linux on the desktop, it's only a matter of time before the Empire Strikes Back and they compromise RISC-V. A devious way, which I don't know if anybody will try it, is with troll patents and bogus patent litigation. My two cents, I hope I'm wrong.

[@First_Principals]

Arm, Intel and AMD have intellectual property that could fall in value if risc5 takes there customers and that would mean in a few years the IP could be bought by risc5 and made open source.

[@philosophyindepth.3696]

i clicked your videos to see you! 😊