RISC-V is the future of computing | Chris Lattner and Lex Fridman

Lex Fridman Podcast full episode: • Chris Lattner: The Fut...
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[@redacted6162]

Im writing a RISC-V targeted compiler at the moment. I have to say that writing the RISC-V compiler was wayyy nicer and easier than its x86-64 counterpart. So even from a compiler-designer standpoint, RISC-V has huge potential!

[@jodeluser839]

Did you build your Prototypen on an FPGA first? That's my goal for now

[@amikomalania3406]

How is it going? Any updates?

[@redacted6162]

Hi, it is quite basic but it is finished. Compared to the x86 compiler, the RISC-V one was much nicer and overall has fewer bugs.

[@low-key-gamer6117]

yeah, its us the hardware engineers who has burden of creating the architecture.

[@backacheache]

As ARM slowly becomes like the thing it wished to overthrow, I am glad a new-alternative is ready to go

[@autohmae]

Ironically PowerPC is probably even more open than RISC-V, but SiFive is working hard to make it easier to get things more modular to allow for more custom designs to be mass produced. I think this is an important combination.

[@donpalmera]

>As ARM slowly becomes like the thing it wished to overthrow, Lots of people seem to parrot this.. but was ARM (the company) ever about being the nice guys? I think it was never the case. People got so caught up rooting for the underdog against big bad Intel that they totally missed that ARM has been a very nasty company multiple times and that the larger ARM ecosystem is full of GPL infringers, highly proprietary hardware with no documentation etc.

[@amigalemming]

Like Windows wanted to become a simple alternative to big Unix.

[@jimitsoni18]

You stole my words mate

[@bighands69]

Without capitalism and a market economy we would still be living in the feudal era with very little technology. ARM is doing exactly what it needs to do and there will be other companies.

[@addielmartinez9120]

Im a very recent computer engineering grad. My last senior design class was focused on creating a risc-v multistage processor

[@BeachCity]

If there are only 5 companies that make silicon, and if RISC-V has no related GPU description, it can't do much IRL. We need inexpensive silicon foundries, and we need a GPU definition with RISC-V. Until we have a complete solution to break monopolistic control over our cell phones and laptops we are stuck with ARM, Intel, and AMD. We need more choices.

[@illdeletethismusic]

@@BeachCity of course the goal is to eventually have all open hardware, but why should risc-v bind itself to a not yet existing gpu design, rather than becoming a force in the cpu space first, taking marketshare from intel, amd and arm, with compatibility to existing gpus being a necessity for the time being, then taking on gpus next, accepting mixed systems as a necessary step on the way for most users?

[@BeachCity]

@@illdeletethismusic If RISC-V requires a proprietary GPU, it isn't cutting any strings. You substitute one barrier for another. GPU's are required for most modern computing. Worse a silicon foundry can cost billions. Universities should be working on very large integrated circuit technology which is very affordable. I would take a 1,000 nm process RISC-5 with GPU all open source if cost was under $250,000 for the silicon plant even if performance was poor. We are locked in to a handful of silicon foundries, a handful of GPU makers and a handful of CPU makers. All this must be solved to be free to make our own stuff.

[@illdeletethismusic]

@@BeachCity very few people go for control over their stuff if it comes at a massive performance cost, what you are arguing for is a solution for a niche audience. if however riscV becomes a major part of one of the component markets, and can sustain itself economically, the push to get another open standard for the other components becomes much stronger, and can grow to a level that OS creators and other programmers will want to support riscV and related components. the goal is free software and hardware, to get there the currently weaker hardware side side can"t be pushed in a direction to make the software for it unsustainable

[@BeachCity]

@@illdeletethismusic The number of critical scientists and engineers at ASML is likely under 1,000. If they were taken out by a hostile actor, there would be no new silicon foundries for a decade and no advancement for longer than a decade. We rely on a very few people who have a lot of proprietary knowledge that can't be easily replaced.

[@frednicholson]

My first job out of college in 1987 was to work on PA-RISC. It was awesome.

[@Mrbeastifed]

This is the first time I felt like I knew more about a CompSci topic than Lex. Shout out my architecture class CS61C at Berkeley!

[@jackzeng7096]

and EE151!

[@BruceHoult]

Maybe Lex doesn't know much ... or maybe he's trying to get his guests to explain for listeners who don't know much?

[@Optimus6128]

@@BruceHoult He said it in the intro of some other podcasts, sometimes he ask simple questions even if he understands, questions that maybe some viewers would have.

[@DeviantDeveloper]

Wow you were at Berkeley and you survived? Pretty dangerous state / area... Did they make you a Marxist?

[@icaropereira3218]

hey, I just watched a Linus tech tips video about it and also knew more than Lex on that, he is probably asking simple questions to let noobs get it, but he is acting too good in pretending not to know.

[@daydaykeyis]

this guy is so happy for the future of computing, smiles nonstop

[@amatureteacher5009]

That's true. The less proprietary the core tech gets the faster the future of computing spreads. He explains well too.

[@DeltaSleepy]

He must be Canadian

[@gavintillman1884]

Amazed to find someone in my year at uni, and an exceptional bass player, at the heart of this.

[@wavecutter69]

What a refreshing interview. This is obviously someone who loves what they are doing.

[@susansmith7030]

Very compelling point regarding projection: seeing a lot more custom chips.

[@astrojames]

i don’t know, sounds a little risc-v

[@axewellll]

A little risc-y

[@kendicloud]

Crickets.....

[@kurokurovich]

@@bytefu lol

[@ionichi]

So "Hackers" was actually prescient. (If we survive '1984' and "Idiocracy")

[@flightmode7655]

if, haha

[@freakinElvis]

The AI says no

[@ongeri]

IFF

[@sfacets]

It's great to see someone passionate about their interests

[@ianboard3555]

One of the reasons why the ARM Cortex parts have such traction is the interrupt controller and the coresight logic. They are very flexible and capable and work pretty much the same across all the Mx parts (there may be some differences like the number of priority levels available). I don't have any particular love or hate for the instruction set, as long as it is well supported by development tools. I am curious about what RISC-V does for interrupt handling and debugging - I confess I don't know much at this point.

[@newsgo1876]

Every startup company says it is the future. After so many years, the single most important skill I learnt is to let it go and focus on what's going on right now

[@DavidWongTianyu]

Very good explanations Chris

[@simonstrandgaard5503]

Finally getting rid of the opcodes that never/rarely being used. Reducing waste.

[@BruceHoult]

The RISC-V base instruction integer set is certainly very small, with just 37 instructions in 6 groups that a C compiler might (and will) generate from C source code for a 32 bit system: register+register arithmetic (ADD, SUB, SLT, SLTU, AND, OR, XOR, SLL, SRL, SRA), register+constant arithmetic (ADDI, SLTI, SLTUI, ANDI, ORI, XORI. SLLI, SRLI, SRAI), load/store (LB, LBU, LH, LHU, LW, SB, SH, SW), unconditional jump/function call (JAL, JALR), conditional branch (BEQ, BNE, BLT, BLTU, BGE, BGEU), and instructions for helping load large constants and absolute/relative memory addresses (LUI, AUIPC). In a very simple embedded CPU that might be all you need, though many would want to add the exception/interrupt instructions ECALL, EBREAK, and MRET and the instructions for reading and modifying Control&Status Registers (CSRRW, CSRRS, CSRRC, CSRRWI, CSRRSI, CSRRCI). So that's 46. In contrast, the 6502 microprocessor in the Apple ][, BBC Micro, Commodore 64, Atari 400/800 and others in the late 70s and early 80s has 56 instruction mnemonics, and many instructions have up to 8 different addressing modes. RISC-V has just one addressing mode.

[@rbus]

Intel is a toxic dump of forgotten instruction set extensions. It’s like Windoze, having to retain compatibility with versions of each. To be fair, x86 code is translated internally so doesn’t waste as much silicon but then x86 is literally a software defined processor and software adds a whole lot more complexity. Simple CPU design means more secure hardware, period.

[@TranscendentBen]

One addressing mode? What addressing mode is that?

[@BruceHoult]

@@TranscendentBen an address in a register, plus a 12 bit offset (+/- 2048 bytes)

[@TranscendentBen]

@@BruceHoult That seems quite limiting, but obviously one can't learn an architecture from a few youtube comments. I'll have to look into it elsewhere.

[@geoffreystearns1690]

I haven't seen the instruction set, but I wonder if I can do double precision arithmetic efficiently in hardware with it.

[@aixsa3877]

Would love to see an ibm open power discussion.

[@Ayyydrianne]

This is my field of study, I love this clip!

[@maksadbek]

It's so good that he smiles when he talks

[@raylopez99]

I once dated a cheerleader and she told me they train for that. I suppose public speakers also can learn to smile after every sentence. It's common to smile when talking in southeast Asia, where they also train from an early age to talk this way.

[@aladdin8623]

@@raylopez99 Or maybe that person is just enthusiastic, passionate and a warm-hearted person. But some people, who can not imagine, such people actually do exist, have to project their own misery into those people's motivations and make ugly allegations, it seems.

[@raylopez99]

@@aladdin8623 Maybe. Did you know your name sounds like "ROT PILE"?

[@aladdin8623]

@@raylopez99 Did you know, that you just confirmed my point about projecting one's negative, restricted perception, while there are clear hints to interpret things in a more positive way? My nick means red pill in english, because in the world there does not only exist the english language you know.

[@raylopez99]

@@aladdin8623 Google "tyranny of positivity', 'smiling depression', educate yourself, move on, nothing to see here.

[@BeachCity]

CPU sans GPU equals no GUI. RISC-V needs an open source GPU in addition to CPU.

[@pentachronic]

Totally agree. GPU is where the heavy vectorized FP math goes. A CPU is the post master. The GPU is mail sorter and deliverer.

[@johnforbes3769]

Absolutely GPU.. and controller chip set is where it is at..

[@dl5244]

Take a look at Xilinx's Zinq Ultrascale SoC line. System-on-Chip style parts are becoming mainstream - it's just part of the implementation details now. Of course you can have some GPU accelerators added to the integrated FPGA fabric with memory controller and cache and a few RISC-V cores and a few ARM cores, or whatever you want! In fact the compiler suite let's you instantiate 'soft' cores dynamically in the FPGA hardware fabric during runtime...

[@pentachronic]

@@dl5244 FYI, Zynq are good but to get GPU performance you need serious FPU performance. FPGA fabric based FPU's typically can't run at the speeds of a hard FPU core. DSP blocks help but you still have a relatively slow fabric compared to standard cell or full custom. However some specialised math tasks can run faster due to hand crafted streamlining.

[@Guztav1337]

Open-source GPU is the dream. Nowadays it is all about lots of computations, all while NVIDIA screwing with the market. With open source we will see more AI accelerators, and many many different hardcore calculation stuff that is very exciting

[@kbcooksey134]

Take a shot every time Chris says the word 'space'

[@johnniefujita]

It is basically the last interface that interoperate the cpu components to respond properly to compiled code. The cpu designers take the instruction set when designing a cpu and the compilers must generate machine instructions from code that is compatible to the chip architecture. The greater benefits from an open instruction set will only emerge as the community becomes more mature, hopefully advancing into a society that have cost-effective end-to-end open chip full architectures and DIY cpu manufacturing technologies. Right now we could benefit from the new emerging companies developing cpu architectures based on the RISC-V instruction set to do not follow the obscurantist path that intel for example took and caused the worsts security vulnerabilities ever. Vulnerabilities at this low level basically contaminates every other level of a computing system.

[@stex5026]

I'm going out on a limb here by saying that the only hope for RISC-V to become mainstream, at least in the apps processor space, is by having China adopting RISC-V as a national standard. The success of a CPU architecture lies so much in the scale of its market adoption and market adoption is such a game of chicken and eggs... You need huge volumes to entice software development, tools development, OS development... So the ongoing tech war b/n US and China is the best thing that's ever happened to RISC-V. Also, one of the reasons for ARM's longevity and success is her tight control of the ISA. No licensees can add or subtract or alter any instruction from ARM's ISA - only ARM can do that and it's done through architecture revisions. So an ARM processor is an ARM processor regardless which licensee produces because they all run the same instructions (assuming they are from the same architecture release). In closed system such as hard drive and other real-time control systems, this might not be as big of a deal. It's safer for Seagate/WD to extend the RISC-V architecture since no one else will ever get to see the software. However, that's definitely not the case with apps processors. For example, one RISC-V implementation may add a proprietary extension for multi-media acceleration that's not available in anyone else's RISC-V implementation. Just imagine what kind of headache that would create for the SW community... Companies like Tensilica, ARC, etc. have been promoting extensibility for more than 20 years. As attractive as it sounds to the engineers, it never worked at scale for the community of the said ISA. Closed system maybe. Open system? Really don't see how that would work.

[@nikoblub3755]

Alibaba bringt Android 12 auf RISC-V-Prozessoren

[@tma2001]

the Itanium lost everyone so much it got labelled the Itanic by the IT press ...

[@blottolotto7648]

haha

[@ByteMeCompletely]

That's funny right there, I don't care who ya are. 8o)

[@theredscourge]

Congrats on winning the favor of the algorithm. KZbin won't stop recommending me your videos all of a sudden.

[@Guztav1337]

That's only because you watch them. KZbin does in no way, shape, or form, recommend the same. Else you would see many videos with billions of views. KZbin creates a bubble, only showing things you agree with, never telling the other side of the story. DO NOT believe that people have watched or experienced the same as you have. DO NOT believe that your bubble is better than another bubble. Be cautious of your thoughts.

[@investworldcamp]

Thnx Friedman u r really a thought designing instrument for me who lives in other sets of environment

[@MyReviews_karkan]

This is huge and not a lot of people realize it. We are now controlled by a couple of companies in terms of instruction sets/architecture, the biggest of them are ARM and intel and AMD. Making an open source instructions set opens the doors for newer companies/entrepreneurs to have a chance. Therefore, more innovations and better technology. We have so many intelligent people who have very good ideas, but can't afford to pay for licensing let alone modify the standard architecture that is set by those companies. You tell them what you need and they design it for you. You can't modify it after that or add to it. Every time you have a new idea, you have to go back to them and pay them to redesign their original architecture, and pay again. When you have a free and open source set of instructions/architecture, then that drops a huge chunk of the cost that's stopping you from showing the world your idea. You can design your own architecture based off of RISC-V at not cost to you (you should donate to them, though). If you have more ideas, you go ahead and redesign it yourself. You reach a good conclusion then you pay a manufacturer (like TSMC) to build it for you. A lot of break throughs could happen.

[@ByteMeCompletely]

Still waiting. How long ago did Patterson birth RISC-V. We're still waiting.

[@anandsuralkar2947]

Waiting for what exactly?

[@fakerfake1491]

How is RISC different from the open source instruction sets that came before? Only the funding?

[@Guztav1337]

RISC-V seems to be where it is at, where people have their eyes. Probably watch the whole interview for your question.

[@80s_Gamr]

RISC instruction sets have been around for a very long time. It stands for Reduced Instruction Set Computing. The idea behind it is his - Of a Complete Instruction Set (on a CISC chip like Intel makes) about 20% of the instructions are used the vast majority of time... and the other 80% of the instructions in the set can have their same results achieved by performing combinations of the other 20% of instructions. SO, why not make a chip that only has those 20% of instructions and in doing away with the additional material needed for the remaining 80% we can architect something highly optimized for that 20%. Since those by a HUGE margin are the instructions being called upon in a typical computer the chip will perform far better than a standard CISC based chip the vast majority of the time... and during the small percentage of times the chip is called upon to do tasks that would normally use the other missing 80% of instructions we will live with the fact that it will not do those tasks as well compared to the CISC (or so the original thinking went). A small price to pay for the potential overall performance gain. Honestly, the ideology worked and for many applications back in the day it really performed well. The old Macs with Power PC's used them as an example. As far as what makes RISC -V different than previous RISC sets... honestly I don't know. Probably a just a more modern incantation of it with some new features added as standard given the demands of a modern world. I really don't keep up on this stuff any more.

[@AndrewRoberts11]

The RISC-V foundation was incorporated in Switzerland, to place the ISA outside of US, EU, and UN sanction regimes, so its USP is it's available to North Korea, China, Russia, ....

[@ByteMeCompletely]

@@AndrewRoberts11 Someday you may regret helping the commies. See ya in the re-education camps.

[@batlin]

Lex's questions and voice here kind of reminds me of Detective Columbo. "Just one more thing..."

[@scottfranco1962]

Small correction: Itainium was a joint project of Intel and HP (referring to the "HP went to Intel for Itainium").

[@slateand808]

Found the HP engineer

[@scottfranco1962]

@@slateand808 Good guess. Wrong, but good guess.

[@williamdavidwallace3904]

Is RISC_V truly a minimal instruction set design or does it compromise on important instructions from the CISC world? Copy bytes is typically a highly useful instruction to have in the hardware. Not being able to store all the registers in one instruction tends to make object code larger for no good reason.

[@Andrei-ng2yz]

Perhaps an analogy might work here: planned economy vs free market. A large group of free-market companies will outperform in efficiency and product diversity a single large company that relies more on its long-term plans than on current market demand.

[@t3h51d3w1nd3r]

I’m pretty sure the colonial fleet was using risc-v when the cylons attacked

[@SCTproductionsJ5]

What?

[@mycommentpwnz]

I've got a background in electrical-engineering, and I have to say, I always thought there could be a much better architecture implementation. I used MIPS primarily, and it just seemed very dated and archaic.

[@billh1337]

Well I think they teach us MIPS in our classes Bc it is easy for a beginner than rather learning xx86 or others .

[@TheEulerID]

The designing of custom chips for particular needs with special additions is a recipe for fragmenting the ecosystem. Also, do not count on RISC V extensions being open sourced. With ARM, it will depend on how greedy they would be in licensing models, and their ability to adapt and maintain that huge developer ecosystem. One thing ARM has been, is fairly light on its feet and listening to customers.

[@tedz7612]

a more general solution that covers specific use cases

[@7Trident3]

Micropython, C++, Arduino and OpenMV IDE TensorFlow Lite. The embedded space has good tools!

[@masondaub9201]

Pfft all you need is C and assembly

[@bighands69]

@@masondaub9201 No harm having other things as well. I love LISP and RISC.

[@user-jb8lx2jq5v]

Situation: There are 14 competing instruction sets. 14?! Ridiculous! We need to develop one universal customizable instuction set that covers everyone's use cases. Soon: Situation: There are 15 competing instruction sets.

[@Guztav1337]

This one is a different matter though. This one competes with the big boys, and is *OPEN-SOURCE.* The thing isn't about a standard. Their goal doesn't have to be a standard. *But they have and they will continue to reduce the cost for a lot of companies and in the end the customer as well!*

[@bighands69]

We need a universal language that everybody speaks. Anybody who objects to the universal language is to be dealt with by the collective. Love and peace is the way forward or else.

[@liliyaversus4051]

@@bighands69 unfortunately universal language doesn’t guarantee people will understand each other. On the bright side with open media and internet we slowly develop universal moral/compassion/understanding and support which is much better (╭ರ ﻌ•́)

[@perforongo9078]

Xkcd. Lol.

[@ByteMeCompletely]

@@Guztav1337 When? Patterson created RISC-V decades ago. Can't buy it at Best Buy. When?

[@madmotorcyclist]

RISC-V is a couple of years behind ARM in it's development in performance and cost. It will be awhile. RISC-V has a problem if vendors have their manufacturers specialized extensions implemented on their RISC-V chips will cause a splintering RISC-V acceptance. ARM avoids that issue.

[@pentachronic]

Here's the biggest issues for RISC-V as I see it. A CPU is relatively easy to design and implement. Where it becomes difficult is the software/firmware/middleware ecosystem. The tools have to be exceptional to make the CPU succeed. This includes Cache modelling, coherency and snoop modelling, and then vectorising compilers that can deal with multi-core. And then you need all the libraries and support of standard chipsets. This will be tough for RISC-V to crack but if enough work goes into it they may have a chance. There are a lot of hungry Engineers in China !!

[@jimbig3997]

Can I buy a Raspberry-Pi-like RISC-V machine somewhere to get started? Never even seen one.

[@flippert0]

Hmm, I think on one hand that RISC-V is _very_ interesting as a technology. OTOH, there's this risc of a fragmented market where you develop for RISC-V but it won't run on another chip supposedly also supporting RISC-V, because it has different extensions.

[@YourIdeologyIsDelusional]

I really, really hope RISC-V becomes big. We really need some ARM competitive RISC-V CPUs to hit the SBC market, the guys developing it really should aim for small business and hobbyists first to bypass the big industry gatekeeping.

[@autohmae]

You are thinking to big at the moment. While SBC exists, it's still expensive. Think smaller: products are slowly starting to ship now which include RISC-V chips as embedded chips and microcontrollers.

[@YourIdeologyIsDelusional]

@@autohmae I'm actually thinking pretty small, relative to the situation. RISC-V is in a precarious spot at the moment, being an open source competitor in an industry ruled by well established proprietary giants. I'm thinking as small as is possible for the platform to see success. To get off the ground, RISC-V is going to have to navigate around most of the embedded market, where they will almost certainly stagnate amidst corporate partnerships, exclusivity deals, etc. RISC-V needs to get price down and speed up, and then offer something unique to smaller businesses and startups. They already provide what the consumer hobbyist market desires, which is to say more open source, open platform technology. The real trick is going to be figuring out how to appeal to smaller business entities that aren't already entangled with the existing proprietary platforms. RISC-V's only real way to see success is going to be by serving a market of similar outsiders. Trying to jump into the mainstream embedded market is going to be a struggle for them because they're not just outside the "big club" but they're offering a paradigm shifting product that could potentially disrupt the current big players permanently. They're not just competition, they're a threat to the entire proprietary model. They need to exploit this fact, rather than fall victim to it.

[@autohmae]

@@YourIdeologyIsDelusional You seem pretty negative on embedded/microcontroller for RISC-V. Have you looked at the list of companies involved in RISC-V and the kinds of products they are trying to use RISC-V for at the moment ?

[@YourIdeologyIsDelusional]

@@autohmae I'm not negative about RISC-V, I'm negative about the state of the industry it's trying to enter. The home consumer market is monopolized enough as it is, but industry is an absolute anti-competitive nightmare. I suspect they're going to hit a brick wall very quickly, and it'll have nothing to do with their product. Early interest will be good, but they're entering a very shallow pool due to the current unregulated state of industry. ARM and other embedded architectures, even x86 based ones, are going to (correctly) see them as a massive paradigm disrupting threat and attempt to start snatching up any industrial market they try to enter. They're going to start having a lot of doors slammed in their face, especially seeing as ARM's already panicking and looking desperate in response to them approaching ARM's pre-existing customers. Anti-competitive and monopolistic behavior is at all time highs, and that is precisely one of the problems that RISC-V is poised to solve. It threatens the entire existing industry, as such existing industry giants are going to try and tighten up their grip on everything if RISC-V starts trending. RISC-V thus needs to repeat the strategy that brought IBM to its knees in the 80s and 90: Start from the bottom up. Don't sell a small product to big industry. Sell a big product to small industry and home users. It's hard, but stagnant proprietary competition will be helpless to keep them from flanking from below.

[@autohmae]

@@YourIdeologyIsDelusional First things first: NVidia is going to own ARM. The fate of ARM depends on if other companies don't seem them as a competitor & can work with them. I would say in the past AMD was in a position they wouldn't mind a big upset in the desktop/server market. AMD because of that has done some work on ARM chips in the past. Now that AMD is busy hitting Intel in the gut I think they might not want to push on that anymore. So that's unfortunate timing. It would have been good if a player like AMD would jump on the bandwagon. Because if those companies would want to move to RISC-V, they could join CHIPS Alliance. They seem to be working on an ecosystem of chips. Not just CPU cores. That being said, RISC-V has a long way to go to get anywhere. For a lot of the reasons you mentioned.

[@dasergioo]

Offtopic, the ontological implication of the question "isn't the universe a compiler?" left a deep impression on me.

[@chromosome24]

oOoh time to start a quick, little, trivial side project...

[@JR-mk6ow]

I didn't knew MIPS was proprietary. I had to learn that shit in college. It was mostly useless. If they are going to teach things at least teach Open standards!

[@smallkitty7887]

Don't be so rude. Okay?

[@kolukolev726]

I was wondering which assembly language I should learn :)

[@favesongslist]

The only help I know assembly language is now is maybe with IoT micro computers, A useful cheap suggestion; look into ESP32 microcontrollers at around $3 that have Wifi and USB built in and lots of free simple IDE's and KZbin tutorials available for some hands on work. check out sites.google.com/site/thecoolbritselectronics/micros/esp32s

[@rockets4kids]

That would be C.

[@matthewpeterson5159]

RISC-V GANG IN THE HOUUUUSSSSEEEEEE!!!

[@boqsc0]

RISC-V you are not in the house.

[@spguy7559]

how can i learn risc-v ? as a begginer . its assembly languge . maybe Rust compiles to risc-v .

[@ByteMeCompletely]

Buy Patterson's book.

[@altoticket]

"RISC is good" -Zero Cool

[@spguy7559]

what ?

[@user-yk5by3uc2b]

Amazing how much thought goes into designing a tiny chip

[@Kenbomp]

I doubt arm will disappear. Though risc sounds pretty cool

[@-argih]

ARM was just to be bought by Nvidia and basically all of the mobile market is ARM, and don't forget Apple is developing a new ARM cpu for the macs, so no, arm will not disappear.

[@dl5244]

@@-argih pretty much any vendor pretending to sell CPU's now has at least one ARM core thrown in the package... ARM cores are nothing special - it's the peripherals and glue logic that makes them shine!

[@Guztav1337]

@@dl5244 One thing should be noted for others who read. The thing with ARM is that they are more efficient than a whole Intel. (not the best on the market for every solution, however almost always more efficient than the intel solution)

[@Teluric2]

@@Guztav1337 efficient? Arm needs more transistors gates to achieve what x86 does check M1 ultra m1 transistor count vs 12gen i9 , M1 needs more than 2X transistors.

[@blahdelablah]

Be careful what you wish for. RISC-V is an open standard, but the extensions do not have to be. Proprietary extensions for RISC-V already exist, and manufacturers will keep pushing them to differentiate themselves from the competition. For example, the "RISC-V Turbo" extensions developed by Alibaba for it's RISC-V chips are proprietary, which is legally fine as RISC-V is BSD-licensed, which doesn't prevent this from happening.

[@ThePandaGuitar]

Should be a top comment.

[@blahdelablah]

@FichDich InDemArsch So? The major selling point of RISC-V is the open architecture, but there is a danger of this advantage being diminished through a takeover by a few large manufacturers, who can then distort RISC-V to become just another proprietary ISA, with the only difference being a few open source elements. To use an analogy, it's like the relationship between BSD and Mac OS X, as Mac OS X was based on BSD but Mac OS X isn't really an open source OS.

[@blahdelablah]

@FichDich InDemArsch It has nothing to do with naivety. The outcomes that RISC-V faces are a result of the design choices they made, especially when it comes to the licence. For example, consider the effect that the licence like the GPL has on keeping software open source. It would have been possible to release an ISA under a hardware-specific licence that was equivalent in effect to the GPL. By doing so, all extensions to the core ISA are open source by default, no exceptions. You could argue this could hamper acceptance by certain business interests, but I would suggest that even if the initial uptake would have been slower, there would still have been a space in the market for this "open source by default" ISA, and companies over time would make use of this.

[@ByteMeCompletely]

Jim Keller is a journeyman computer architect. Patterson has been slapping the monkey in academia his whole life. Patterson has been working on an ISA for forty freakin' years.

[@klam77]

Risc-V anyone can build chips targetting this instruction set!

[@johnforbes3769]

Hopefully it pans architecturally like Unix flavors have.

[@killahsin7106]

i dont necc know that risc-v is the future however it is going to lead to some really good shiz.

[@pureheroin9902]

Yeah, I think we should get comfy, this may take a while. I hate Google, but it'd be nice to see a big company like Google make a reference design phone using riscv

[@bighands69]

@@pureheroin9902 Google would be better if it had competitors to keep it on its toes. Most of these tech companies that are socially based are very new with little competition. They would not be so political if they had a rival to keep them running.

[@markteague8889]

I find myself wondering, with Apple's recent decision to abandon the Intel x86/64 standard in favor of their own ARM designs (i.e. M1, M2, M2 Pro, etc.), why Apple didn't choose Risc-V for the future CPU architecture on which to base their future products? It would save them the licensing fees that they must pay to ARM in order to manufacture their own custom ARM designs.

[@autohmae]

because they paid one single very large fee to do whatever they want with ARM themselves and make their own chip designs, they already had that for mobile devices, so it's easy to do the same for laptops/desktops.

[@catchnkill]

@@autohmae More important reason is that Apple wants to use manufacturing IP developed jointly by ARM and TSMC.

[@autohmae]

@@catchnkill TSMC makes RISC-V and AMD64 chips too, is their really something special they do for ARM ?

[@askii3]

When Apple made that decision, RISC-V wasn't complete enough yet to design a new product line around. The solidification of v1.0 vector extension spec of RISC-V happened at the end of 2021.

[@Tapajara]

It is unfortunate that they are calling a "Programming Model" an ISA. A Programming Model is more than just an Instruction Set. It includes Registers which are not Instructions.

[@guccifer2]

Don't get your hopes up. :salute: to the Sifive team but there is no open source ddr memory controller for the foreseeable future. Kinda defeats open ethos if you cant access memory without a NDA.

[@autohmae]

PowerPC is more open than RISC-V at the moment. Like pretty much any start up CPU instruction, they'll have to start at the bottom, embedded and microcontroller chips first.

[@gedw99]

So it’s sort of like open cores in Sweden ? You need UDP in your chop then you buy UDP blob that magically gives your standard rISCV chip design UDP ?

[@dl5244]

I'd think a typical implementation using ARM cores would involve multiple licences (for each peripheral). Doesn't this get things rolling with solving one of the more challenging pieces? IE. If I can implement this RISC-V core in my FPGA without contracts nor royalty and just copy+paste, that'd be pretty good incentive

[@autohmae]

@@dl5244 RISC-V ecosystem needs time to grow and it all depends on companies adopting it and using it for real every day products.

[@georgeindestructible]

Louis Rossmann's voice sound very similar(youtube search him).

[@turanamo]

lol! Hi Five! KZbin is a small world!

[@HablaConOwens]

I hope to see a new OS built from the ground up. Maybe we can get a new phone out of this by 2030

[@EdwinFairchild]

I understand the great thing about open hardware , but is that indicative of quality , so is RISC V right now better faster , more efficient etc... Than ARM? And what is to stop a company who takes this open standard and start modifying it and improving on it but making these improvements their own held secret and where back at proprietary cores again...???

[@jpalmz1978]

I suppose a license for using the technology could mirror how the GNU license works - the ‘catch’ is the modifications are then republished back. There are companies that have been criticised for not sticking to the system (I think Android). To be honest it could allow more competition in the field, but another obstacle is the US - development of certain processors that can be classed as potential military applications (as this does not just sit with processors - It can be any US standard) require a ‘license’ to produce and sell. It can all get really tense and messy

[@SouravBagchigoogleplus]

With time ARM instructions are becoming complex. Now a days ARM instructions are as complex as CISC.

[@0xhiro]

When you make chips, everything is a compiler

[@dhruvamukhopadhyay1931]

I heard about the new Wang's law coming up, rendering the Moore's law obsolete.

[@bighands69]

I had to google that and then roll my eyes.

RISC-V is so great, shame that web and high level devs will squander whatever gains these marvels will bring

[@Little-bird-told-me]

As Chris Lattner said RISC-V is not open source, it is an "open standard" for the architecture

[@autohmae]

It's as close to open source any document could be, the specification documents are in: Creative Commons Attribution 4.0 International License And the development processes are similar to open source software development.

[@johndebord7802]

I don't know anything about hardware. But can someone answer these questions? 1) Is it possible to embed cryptographic hash functions into a chip? 2) Is it possible to implement a chip that can only talk to the same type of chip? Meaning that the chips will know if they are the same, and one chip can't lie about it being the same (as well as a human can't somehow tamper with the chip to fool the other chip into thinking it's the same)?

[@horus909]

1) yes, this is what bitcoin miners are entirely built of. 2) not really. You can build some function like a hash that can only be done very quickly with dedicated hardware though. Someone wanting to impersonate your chip would need to simulate it, with much more powerful general processors(100x faster) to be able to reply as fast as the chip with the dedicated hardware. It would secure against most people, but not someone with a lot of money available.

[@johndebord7802]

@@horus909 awesome thanks!

[@wikingagresor]

Embedded cryptography is a catastrophic idea. Look up the problems with Apple and their T2 chips. Inside there is a code to boot up system and decipher the hard drive. When this chip goes bad it bricks your entire Mac and because you have soldered in ssd, your data is also unrecoverable.

[@horus909]

@@wikingagresor You are talking about an embedded hardware key that can't be recovered. I agree, bad idea. Dedicated crypto silicon that just processes the algorithm is different though, with the key held in memory. My example didn't even use a key that could be lost.

[@aliuzel4211]

1) Yes 2) No idea.

[@ByteMeCompletely]

100 years from now, RISC-V will still be the future.

[@justinbrown2410]

What is the tradeoff between RISC-V and Arm chips?

[@justinbrown2410]

Are there any advantages that Arm chips offer that RISC-V cannot?

[@rjordans]

​@@justinbrown2410 a long track record to convince management that they work

[@enjoypolo]

What can RISC-V do, that other architectures (like x86, ARM) cannot? I'm especially curious of the potential use for smartphones (I need a laymen explanation, thanks :)

[@diamonddave2622]

RISC-V doesn't do anything that x86 or ARM can't do. However, the instruction set is open source which means no royalties or license fees have to be paid. An OEM could therefore reduce its chip costs and have cheaper custom chips that are optimised for their product. Optimised CPUs like the Apple A series run cooler and are less power hungry making them ideal for mobile devices. Most OEMs have to use 'off the shelf' CPUs that might have features that they don't really need, using power.

[@AndrewRoberts11]

The RISC-V foundations is incorporated in Switzerland, so the standard, and tool sets are all outside US, EU and UN sanction regimes. Offering North Korea, China, Russia, ... access to a cleaner than MIPS V, RISC ISA, they can incorporate into domestic, appliances.

[@ByteMeCompletely]

@@AndrewRoberts11 And military applications. Some day you may regret helping commies.

[@greenbean5186]

@@ByteMeCompletely how can dumb hogs survive in the real world?

[@aeroscience9834]

Is RISC-V more BSD “open” or is it like GPL? Cause if not, any risc-v derivative that does make it could be corrupted.

[@hansvetter8653]

The Touring machine has just 3 instructions: invert shift-left, shift-right.

[@apexvadeor3670]

When can I buy stock?

[@TheHellogs4444]

I thought RISC-V was open source? Most companies will switch to this, and small startups/unis already use it Edit: AMD first

[@apexvadeor3670]

@@TheHellogs4444 if they have an IPO I’m buying and ame is going to shoot yo next week Bc of earnings i have some options on it I boight

[@TheHellogs4444]

@@apexvadeor3670 A fellow WSBer

[@apexvadeor3670]

@@TheHellogs4444 nice to see a member

[@TheHellogs4444]

@@apexvadeor3670 ONE OF US

[@gofudgeyourselves9024]

Came here after the flutter forward event after flutter support for it

[@FallLineJP]

RISC always has been, and always will be, the *future* of computing ;)

[@YourIdeologyIsDelusional]

The irony here is that RISC-V, being open source, could supplant muscular desktop CPUs where CISC designs tend to be superior, simply because someone could design a CISC shell around it and make what would effectively be CISC-V. The more compact and flexible they make their design, the more this architecture will be able to cross markets. The beauty of open source is that anyone with the know how and means can take a good foundation and build on it for their use case.

[@dl5244]

@@YourIdeologyIsDelusional imho RISC vs. CISC is all about the compiler. Neither hardware devs nor firmware devs care much about which it is. Just use the right compiler for your processor. The assembly is all that's different - but it's always a little different. There usually just a few lines of ASM boot code you copy from a reference manual or snip from compiler output

[@ByteMeCompletely]

@@dl5244 RISC vs CISC is all about religion. Neither is a clear performance winner.

[@dl5244]

@@ByteMeCompletely I've developed firmware on both for >20yrs. I agree (b/c I'm architecture agnostic - as my previous comment tried to outline) btw: "performance" is a nebulous metric and not the only one!

[@eriklintsev]

Future indeed!

[@rbus]

Had a funny idea listening to this. As Android opened up a new world of repurposing old phones and in some cases devices already running embedded Android for adding completely new functionality. Wouldn’t it be cool if RiscV opens the possibility of buying appliances with open firmware to tweak as you like. Granted there’s some level of danger here for say kitchen appliances but I’m always thinking of features I wish I could add myself.

[@AkkarisFox]

@@richardshane456 please explain.

[@rbus]

@@AkkarisFox I think poor Richard is asking if anyone has any girlfriends he can borrow. 'Ole Lucy's on her last leg

[@AkkarisFox]

@@rbus sorry i asked.

[@AkkarisFox]

​@@richardshane456 could you rephrase this?

[@AkkarisFox]

@@richardshane456 I think we will modify the human brain reward circuit because we will become bored of everything. This could cut the root of this hydra we call addiction.

[@pavelbaidurov228]

RISC-V will be pain in the ass, it is same as ARM, yes, you can use free license but in order to get "qualification" you need to pay, and all of the ok drivers will be only for qualified versions.

[@amatureteacher5009]

RISC-V is putting x86 ARM at RISK which is healthy for the consumer.

[@AckzaTV]

SOUNDS PERFECT FOR EOSIO blockchain

[@jaycorrales5329]

Sun Sparc risc architecture is open source since 90s, so not sure why all of a sudden this new risc-v has done smthg remarkable or new? How long does it take to go from design specs to chip production, e.g. how complicated (cost and time) is that process? In order to differentiate from fpga's, what are the performance comparisons numbers? What other companies are adopting r-v, and what are they doing w it? Where is the state of Linux Operating Systems in utilizing r-v? Does it address the von Neumann bottleneck? So now you need a whole bunch of new open IP cores to support this latest iteration of r-v architecture that already existed for current devices, but re-written?

[@BruceHoult]

Sun open-sourced 32 bit SPARC but never 64 bit. And then they got bought by Oracle. Nuff said. SPARC is also not that great. RISC-I and RISC-II had register windows (and SPARC was developed from them) but the Berkeley people later decided that's a bad idea and RISC-V doesn't have them. Cores implemented in FPGAs typically go 50 MHz to 100 MHz. I think the slowest real RISC-V chip is 108 MHz (GD32VF103), with lots around 300 to 600 MHz (FE310, K210, PolarFire SoC), and the 2.5 year old Linux FU-540 at 1.5 GHz. The FU-740 will be formally announced in a couple of days, and is expected around 2.0 GHz, competitive with Cortex A55.

[@kentheengineer592]

Language Isnt Nessecary to Achieve the Same Goal Of Language Its Just One Means to the Same End Goal

[@wmrieker]

0:55 I need a license to make an x86 compatible processor? I thought any company can make a processor with a given instruction set. I always thought the are patents are on implementations.

[@juliusfucik4011]

Doubtful. Patentlaw would easily allow patenting a set of instructions and how they can work together. AMD pays big bucks to use Intel X86 instruction set... But you may be right.

[@nachiketshelar8114]

What I don't understand is whether or not this 'open hardware' could cause patenting and commercialization issues. Any opinions?

[@BruceHoult]

The main parts of the RISC-V instruction set are all very carefully based on ideas that are so old the patents (if any) have expired. Almost every major computer company has joined RISC-V International and in the membership agreement they have to say that RISC-V does not infringe any of their patents.

[@catchnkill]

RISC-V is not open hardware at all. It is open instruction sets only.

[@AbhTri-kq8hc]

x86 and arm have been around 30+ years, I don't see any change in architecture coming. Especially, when apple has signed deal with arm till 2040

[@etorawa9367]

Imagine a toaster that can mine or even stake cryptos while idle......yeah man...this is going to be AWESOME!

[@jaycorrales5329]

Toaster is mentioned mark @9:42.

[@WyomingGuy876]

I want a toaster that constantly asks me if I want some toast......

[@baki9191]

Little surprised Lex knew so little about this topic. Some viewers might think that he's asking these types of questions to help inform the audience but in reality, even the questions themselves are asked as if he has no idea as to what this is.

[@vintagekyoshodotcom]

Risc is what I’m using more, I just purchased a risc laptop.

[@Ayyydrianne]

My professors would be upset with you when you said “code” and “HDL” in the same sentence LOL

[@peters972]

Will gpus and cpus merge and use risc-v? Will neural networks be part of that somehow?

[@arnabbiswasalsodeep]

At this point, that's a very hard thing to predict even if we can be hopeful for that. Risc-v is an instruction set and for cpus. GPU would use different instruction sets. Heres some segregation to understand it better:- 1. Risc V is instruction set, aka language. It tells how to say and read "hello" and not read it as hai-lou 2. Implementation is on the companies like SiFive who design the architecture in such a way that it consumes less power or is faster. Like "lets place this multiplier unit close to this other unit", etc. 3. Fabrication labs like TSMC take the design and use their way to manufacture it. Ofc, without saying, point 2 & 3 are very closely knitted. TSMC in this scenario gets to say "yes, we can do this and at 7nm and with 70% yield and the voltages you wanted would be around in this range" And here's where your question is divided into different parts, risc-v is just point 1 for cpu, you need the same for GPU and even neural processing units (npu) nowadays require specialised hardware/instruction set. So based on how the other part is done and how they can make it interact with each other (like how AMD did with Apu & after Xilinx inquisition they might do for fpga as well)

[@peters972]

@@arnabbiswasalsodeep thank you!

[@RogerKeulen]

Next thing: Better programming languages for the +1024 cores world.

[@bighands69]

What is really needed is applications for the infinite core concept.

[@qbitsday3438]

To put it in lay mans terms as an example , if x86_64 dose some job in 10 instructions , RISC processor dose the same job in 5 instruction.

[@UditDey]

Absolutely not lmao that's absolutely not what any of this means, cisc archs like x86 will actually do the same job in fewer instructions, the benefits of risc archs are different

[@qbitsday3438]

@@UditDey meaning of lay man looks like not in your dictionary

[@russianbotfarm3036]

@@qbitsday3438 you got it the wrong way around.

[@ByteMeCompletely]

Don't quit your day job. You suck at computer architecture.

[@vernearase3044]

So, when you say the future of computing, you mean a non-locked down instruction set architecture. That's got nothing to do with its speed or performance, but rather that anyone can produce some mutant version of the standard without restriction. Doesn't that put RISC-V in the Android space of fragmentation then - where all the smartphones are running Android but on chips and OSes with slightly different implementation details?

[@karthikbalakrishnan4473]

go bears!

[@klam77]

sproul drunk.

[@siouxperirish]

Fargo reference or the ‘85 super bowl?

[@sahhill1910]

RISC-V is good in theory but it's still 4-5 generations behind ARM and then there is the issues of things possibly being forked and the cost. For example if you picked up the latest Raspberry Pi and RISC-V chip, you'd get 2x performance for half the price for the Pi, which is ARM based. It's nice to have competition, but RISC-V isn't the open source revolution that we think it is like it was for software because hardware is expensive even if the instruction set is "open source"

[@johnbarnesNnaptown]

I don't want to know how they make the hotdogs I just want to eat them PAUSE.

[@bighands69]

Most people feel the same a long as the hotdogs are not made out of human brains.

[@johnbarnesNnaptown]

@@bighands69 Soylent Green is people

[@JasonB808]

Wonder if Apple will be using RISC-V or has been using RISC-V. It would make Apple to not have to rely on ARM. Especially when Apple is shifting their Mac to Apple Silicon.

[@Peter_S_]

ARM was created by a partnership between Apple (potential high volume customer), VLSI Technology (fab), and Acorn (designer).

[@Teluric2]

@@Peter_S_ Apple M1 would be nothing if they would have not hire that chip experts to design M1 abd buying pasemi. Apple is looking for risc v designers

[@Roedygr]

There are 10 apps for every conceivable need to run on Intel, There are 0 for RISC 5. There is a lot of work to go before RISC 5 can supplant Intel. Perhaps for servers with a limited number of apps.

[@DTheHAge]

Should be solved by the fitting compiler. Or an assembly translator, than you could convert the object files generated by most native compilers and afterwards use a RISC-V assembler to finish compilation.

[@-argih]

RISC-V is currently used more in ASICs than in general purpose CPUs, Western Digital for example is already using it on the HDD controllers.