Building a 6800 CPU on an FPGA with nMigen (part 1)

[@vimalsheoran8040]

This is the gold that youtube never recommends but, wants you to find out

[@emrahe468]

I'm feeling the same most of the time. And its algorithm "intentionally" directs you to crappy content with a higher bias.

[@fathomisticfantasy2681]

Right? Where has this been all my life?

[@Lazrdo]

Actually Sir. your project aren't pointless at all. Keep it up. People like me are learning so much from you even if you aren't an organized teacher in your lessons. BUT GREAT GREAT LEARNING EXPERIENCE FROM YOU Sir. Wish you all the best in the life Sir.

[@gsuberland]

You have no idea how perfectly timed this is! I've recently been complaining about the lack of tutorials that focus on Migen / nMigen for folks who haven't got a ton of FPGA experience. I'm very much looking forward to following this series.

[@TheBodgybrothers]

Comes for FPGAs; gets pinball history

[@bernard2735]

Awesome project. I still have my MEK6800D2 from 1978, it will be nice to follow along with you as you build this.

[@kevincozens6837]

I was checking out some of your other videos when I saw the reference to 6800 so that brought me here. nMigen sounds like a similar idea to MyHDL.

[@vincei4252]

Hi Robert, very cool to see the latest project. Looking at the lazy edges on signals on the datasheet and considering the high clock frequencies in current components with their fast edges, I'm wondering whether you'll need to make accommodations for the fast clock edges when interfacing the FPGA solution to the the 6800 socket and the long transmission lines it will drive. I remember watching a video somewhere where one of the old hands was talking about receiving newer CPU chips from a vendor years after their board had been designed and the newer chips not working at all because the CPU vendor had significantly improved rise times for all edges which caused the old circuit board to be unusable because it was a spitball design that depended on the clock edges to be pretty slow. Just a thought. I'll try to track down the video in question - I think it was from one of the guys that guested on EEVBlog and the AmpHour.

[@vincei4252]

Here you go. Jack Ganssel is his name. Here's the link just in time for Christmas :-) kzbin.info/www/bejne/g3vTdXmkh7aqbtU Yes, I do have a copy of the Handbook of Black Magic.

[@RogerBarraud]

@@vincei4252 Jack Ganssle. You can select slew rates on many FPGA output drivers nowadays.

[@TomStorey96]

Will you be doing more on your RISC V project? That was really cool, but it seems to have been replaced with new interests? :)

[@johalun]

Welcome back! Interesting project 👍🏻

[@julian7333]

Once you have a working 6800, you could add the instructions and IO for the 6801 and 6303 processors (and do the minor flags change for the CPX instruction).

[@ratinthetub5048]

Oh, this is something I'm really interested in. I'll most likely be following on with this and trying to implement one alongside

[@JacklapottTv]

Nooo dude the project is not pointless at all, i'am super excited :'(

[@BobCollins42]

Thanks for an interesting overview. The operation would be much clearer to me if you started with the state machine.

[@AkatlaLet]

Yap!

[@pixelflow]

I for one welcome our fpga-running-8-bit-cpus-with-5volt-level-converters-on-DIP-adapter overlords!

[@PeterCCamilleri]

Cool idea. On that note, what became of your project to build a RISC-V without using an FPGA?

[@christophernetherton9389]

Thank you for the link to your notes. Have never used anything other than Verilog and am very interested in this!

[@schr4nz]

It's interesting that you decided to show off the pinball machine, not 3 days after I was watching pinball machine videos, specifically about the Xenon machine, because KZbin recommended me videos about Suzanne Ciani, who is a synthesizer musician and wrote the sounds for it. It's not like KZbin recommended me this video based on that, I was already subscribed to you, just a strange/interesting coincidence.

[@UpcycleElectronics]

A rather beginner 101 question, but is the hand drawn description at the end considered a "pipeline?"

[@williamskiba6786]

what ever happened to the rest of the zork cpu videos? I see only up to #6

[@RogerBarraud]

Pretty sure the Data bus contents on a read cycle are latched on the falling edge of phase 2, not the rising edge of phase 1... but I might be 6502-ising here?

[@EngineeringVignettes]

I started out with VHDL, moved to Verilog and am now at SystemVerilog. The last option makes the most sense to me as a firmware engineer... Good for simulation testbenches as well. There was a C based FPGA language kicking around about 12 years ago, never seemed to become popular though... I have never heard of the Python based language that you are going to use I will check it out. It's up against tough competition though, the 2 V's are like the thing that would not die 😋 Cheers,

[@EngineeringVignettes]

@MrMagooo - Thats what I get for typing this late at night... mixing my SystemVerilogs with my ActiveHDLs... fixed.

[@EngineeringVignettes]

(Update) - Found those older C-based languages; they were System-C and Handel-C. Both are defunct projects now. A new C-based HDL Synthesis tool, out of the University of Toronto (LegUp), seems to be the new kid on the block for representing C.

[@robertf981]

@@EngineeringVignettes SystemC is hardly defunct; Mentor's Catapult and Cadence's Stratus are High Level Synthesis tools that work best consuming SystemC. NEC Cyberworkbench and Xilinx VivadoHLS also work with SystemC. It provides the conceptual parallelism that C or C++ based implementations cannot. I've used the Mentor and Cadence tools.

[@davidclift5989]

@@robertf981 but that's the issue with all these software languages being used to design hardware, they are not inherently parallel in execution. Both VHDL and Verilog/SystemVerilog are written on the backbone of parallel execution. People should stop confusing software languages with hardware description languages.

[@meredithcaveney1209]

Hey Robert, Thanks for posting these videos! It's great to see all the tools being used together. To anyone that could help: Is it possible to combine a project mostly finished that is written in Vivado using Verilog with an nMigen module? For example, could you use nMigen to import numbers from a text file and feed them into the Verilog project? And would it be any easier to use one or the other? Thanks again!

[@vasili1207]

Do you programme for the MISTer project? If you do not maybe you could look it up and see if its up you're street

[@RogerBarraud]

11:20 Pretty sure that only works if it's fabbed on a spherical die...

[@MichaelFJ1969]

@Robert Baruch : Thank you for making this video series. You have introduced me to the world of formal verification, and the rabbit hole is very deep indeed! Anyway, thank you for being such an inspiration! I'm now writing up my own experiences (using VHDL) here: github.com/MJoergen/formal

[@duality4y]

what level shifters did you use, i want to use some in a project and am currently doing research to see which fit within my project :)

[@RobertBaruch]

Looking at the 74LVC8T245 (8-bit) and the '16T245 (16-bit). These may turn out to be overkill. For example, the address lines are 16-bit tristate output, 3v3, so I don't have to care about dropping a 5v signal to 3v3. If the thresholds are with me, I can just use an ordinary TTL tristate buffer (such as the 74LS541) for these.

[@dsodso1664]

Any chance to make a faster x86 core faster than ao486?

[@teitoklien]

First ! Glad to see your new video Robert Have a great day !

[@MeSlimyboi]

with only 3 comments, I can agree with you being the first

[@TheBodgybrothers]

Being the first is the highest of skill

[@mathlevr]

Hey Robert. Cool shirt. ;)

[@Aemilindore]

Howly shit. This is changing my world

[@surprisingstuff]

Brilliant!. Subscribed.

[@douro20]

flipperservice.at makes replica replacement boards for Bally pinball machines.

[@craigmanning2439]

6800 Well nice for any one who wants to repair a Bally or Stern pinball MPU. Ten of then sitting in my parts supply. Now getting 5101 memory. That is a different question.

[@duality4y]

Verilog ugly?

[@esra_erimez]

What are the differences between a 6800 and 6809/6811? I'm genuinely curious.

[@TomStorey96]

The Wikipedia entry for the 6809 has some detail on the differences between the 6800 and 6809, perhaps that will answer for at least some of the differences. Otherwise, see if you can find the datasheets for both and have a quick skim through.

[@tommythorn1336]

Funny, I was thinking about this too. I spent my youth on a Z-80, but I think the 6809 had the best ISA from the programming/compiler point of view. I did build a dev board for the 68HC11 (surprisingly easy), but I never really did much with it, bummer.

[@esra_erimez]

@@tommythorn1336 I learned on a TRS-80 with a Z80, but like you I agree that the 6809 had the best ISA.

[@EddieSheffield]

@@esra_erimez I had a TRS-80 as well, but it was the CoCo with the 6809. Doing assembly on it was so clean. Then I got to college and did some 68000 (which was wonderful and just felt like a suped up 6809) and 8086 which was a complete mess. I've always wondered what the PC landscape would look like today if IBM had used the 68K instead for their first PC.

[@MrGeorge1896]

So it took me 6 mins to figure out you are NOT talking about the 68000. Maybe I need some glasses...

[@tonupif]

Спасибо тебе дорогой американский друг.

[@MickeyD2012]

I can't believe a new 6802 costs more than the average new Intel chip. What has the world come to?

[@thomaschu4812]

I don’t think 8k LUTs is not enough to emulate a 6800. You need to simulate the design first.

[@w.maximilliandejohnsonbour725]

Interesting...!!!!!.

[@smunaut]

Watch out ... auto-direction bidirectional level converters never work properly ... avoid at all cost.

[@irgski]

Seem to be having trouble installing the python extensions “pip” and “venv”. Any clues or help?

[@AntneeUK]

I'm gonna be _that guy_ who questions pronunciation. Sorry... I've always known it as g-eye-gher, not g-ee-gher. Which is right? I'm sure it doesn't matter, mind you...

[@JensAndree]

It's G-ee-ger. I'm a multi-lingual Swede with extensive knowledge in the Germanic languages, for reference. Most Europeans pronounce it correctly but for some reason the British pronounce it like a Geiger counter, which is incorrect in the case of H.R. Giger. If he'd been born in the UK it'd been pronounced like a Geiger counter though...

[@AntneeUK]

See, now I'm glad that I asked, @@JensAndree! Thanks

[@bennguyen1313]

I understand migen became nMigen which became Amaranth HDL.. but any thoughts how it compares to Chisel? I have a SmartFusion2 device, so technically it's not officially supported by LiteX.. so I'm kinda starting from scratch. Unfortunately, much of the learning material is a bit dated* *2016 whitequark Implementing a UART in Verilog and Migen LambdaConcept tutorial from 2020 is only accessible via internet archive lab-sticc mic-sec-2022 2020 vivonomicon Learning FPGA Design with nMigen RobertBaruch / nmigen-tutorial libre-soc HDL_workflow/