Sequence Detector (Example)

[@sandiplow]

It's been 8 years but still relevant, helpful and easy to understand

[@careerwithmann481]

you are absolutely right brother.

[@tejaaduri7885]

Yeah bro

[@TastyLaserCakes]

You have gotten me through so many homeworks and tests it's not even funny! Trust me, I've been sharing you with my friends. Great job and thank you for posting these.

[@mpelalidiko]

thank you so much for this video. absolutely perfect explanation with the "Has - Awaits". so simple and intuitive. Was struggling for 2 days to figure it out with normal university books. subscribed.

[@bojanadrangova7189]

When designing a sequence detector, but with Moore state machine, how do you get the output y (cause it shouldn't be dependant of the input x) ? In this case will it be just Qa ?

[@kittyCatCutieCat]

There is no need for the state s3 , we can directly connect s0 with s2 for 0/0 and put a loop on s2 for 1/1.Correct me if I am wrong.

[@rejilrajep3641]

same thought here

[@leoncss]

I share the same thoughts, but is it correct? But if we only have 3 states, how do we come up with the state table as we need 2 Flip Flops. Maybe that's the reason for the s3.

[@shubh2317]

fourth state of the F/F could just be a dont care, dont cares are possible in state table

[@zackm5693]

Yes you're correct, it's a redundant state (therefore functionally equivalent to S2).

[@rahulsaxena5015]

State reduction is explained in the next video itself.

[@Legend_Hunter_Original]

Hands down the best resource on internet to learn Intro To Digital Logic, Thanks a bunch .

[@garthenar]

Just got a 97.5% on my final because of this channel.

[@imranabbasi9535]

Nerd

[@santoshpal8612]

Kis clg me itne marks milte hai bhai 😅😂

[@chandanacr3459]

Sayi

[@lilMartian78]

Itne toh agar phone aur book v dedo toh tabh v nhi aate

[@teothegreat3439]

i am watching this three hours before my exams....you seriously saved me. Many thanks !!!

[@yashkapoor5894]

Clear explanation. Amazing!

[@vechamvidya4499]

Explanation is just amazing...no words to describe

[@lastborn4sure]

firstly I will like to appreciate the brain being all these videos, I want to confess that watching this videos have really changed my orientation about digital electronics. God bless u sir. please my request is that I will like to have a lecture like this using JK flip flop instead of DO flip flop. Thank u

[@lastborn4sure]

+Neso Academy I will be the happiest man on earth if that could be done soon as possible bcause all your lectures has been interesting and it's really giving me confidence on my forth coming exam. thank u so much

[@ashwinb9572]

sir have you uploaded the same problem using jk flip flop....? it l b much useful fr me

[@ahmjazly]

The state diagram u hv drawn is for Overlapping??

[@santhoshk8703]

Fantastic explanation broo..... Far better than coaching..

[@tonee899]

I would have failed my semester without your videos, really, thank you very much!

[@katiecatalano7306]

what would the finished clock look like at the end of this implemented circuit? I'm not certain if this would be synchronous, all coming from the same clock pulse, or asynchronous, or how to know. thank you so much for the amazing lessons and explanations. Your work makes a huge positive impact for me.

[@arjuns2219]

u r a life saver SIR!!!

[@sadiqlawal7335]

thank you very much for this video. it really helped me..how i wish i have seen this before my midterms...you really are a good teacher...

[@15PinkDiamonds]

i passed my class because of you. thank you fam

[@Brian-mf3ry]

love your videos but this video and the previous one were extremely confusing. can you please explain more about overlapping and a more detailed explanation on how you got the state diagram?

[@asfandyarsanam8807]

My apny class fellows ko b ap ki tarah samjaya tha state machine thank u sir

[@4haddi201]

mazza a gaya kya padate ho sir....u rock

[@damazingwundawuumaaan4441]

can you kindly answer how it is determined that we need 2 D-flipflops to implement this circuit>?

[@samandrews7600]

in non overlapping case when four 1111 comes ,after three consecutive 1 was noted out put was 1.and again it started from next 1,but question was to find three or more consecutive no of 1's ,it makes a doubt that when four consecutive ones comes output should be 1 only or 0

[@AryanKumar-qo6fi]

I have no words. Ur amazing👌👏😁

[@dularapeiris2337]

thank you very much for the tutorials.i have learnt lot of things from your lectures.this covers my syalabus and this is very easy to understand too.

[@Toko9441-g9u]

Won't just three states be enough for the sequence detector? at s2 state if next bit is 1 the next state is s2 itself and o/p is 1 Forever grateful for the playlist!

[@Stefan_2117]

Yeah you are right, even I was confused with that needless extra state

[@husseinghannam1663]

your videos are so helpful, thanks a lot

[@sepehrgolestanian6161]

I think when we are in S2 and input is 1, make output 1 which means we have detected 111 and get back two s2 which means we've already seen 11 and waiting for another 1. it's like slicing the adjacent 1s into windows of 111s.

[@user-dz6zd9zk2f]

exactly the diagram should have only 3 states in total

[@user-dz6zd9zk2f]

but no , wait a min if you that you wont be able to write the 4 states as qa and qb are 2 varaiables of the present state and there must exist 4 states to complete the table

[@adeirman2705]

@@user-dz6zd9zk2f yeah, you can use QA QB X until 1 1 1 and when QA QB X = 1 1 0 and 1 1 1 or that means QA and QB is 1 1 respectively or when S3 happen, you assign QA+ and QB+ = X (don't care) because the S3 is unlikely to happen, thus if you use D Flip Flops you can assign QA+ = DA and QB+ = DB or when you use T Flip-Flop you can also assign TA and TB as X (don't care).

[@leonsutram]

@@adeirman2705 Was looking for exactly this in the comments! Luckily i found ur conversation about it; was really confused why he uses 4 states in a Mealy where 3 would be enough.

[@vikramank4521]

Sir there is no. Need for DA and DB K-map. Because DA=QA+ and DB=QB+.So we can directly write them from next state.Are I right ?

[@rajkaransingh4302]

thank you soo much for the video i just want to know whether we can use any gate to impliment the assigment table or not

[@muzammalhussain4887]

I think there is a mistake in the output of nonoverlapping. when we first 001 then the output should be zero and after that, the next sequence should start and in the next sequence there are two 1's so the output should be zero again not 1. correct me if I'm wrong.

[@matiasmarro7985]

Im from Argentina and i study Engeneer Electronic you´ve saved my year with this videos! Congrats!! U has made an amazing job.

[@tanishrane]

awesome, nice explanation

[@thilakshetty5598]

In the S2 state if we get 1 as input we can take next state as S1 which will be easier since we will have only 3 states.

[@sagarikanangia507]

if we create a self loop at s2 with input 1 and output 1 then we wouldn't have to use state s3,right?

[@retrokon]

Thank you, this was very informative.

[@saibunny1253]

thank you sir for your videos ❤ sir we can detect the same problem by 3 states only .

[@anusuyanallathambi248]

Is there really a need for the S3 state? The S2 can keep producing high output as long as the next bit in the bitstream is 1 right?

[@hardnachopuppy]

Yes there is no need for s3 This is why we need to use state reduction before designing the circuit

[@5aledSefarat]

I do not understand: Is this a Moore Machine? If yes, then why is the output influenced by the input? If it is a Mealy Machine, then why is the number of states four while the number of bits is three?

[@hardnachopuppy]

S3 state is not needed

[@ryszardsinius4828]

I truly love you man

[@qwerty5850]

state c and state d are identical so can we reduce them ?? and if we can , how will we draw the state table??

[@ayadabdulkareem6456]

True ... i try to solve it before him and had reduced it to 3 state only ...

[@rejilrajep3641]

connect s0 with s2 for 0/0 and put a loop on s2 for 1/1

[@unaabadi454]

i want to say thank you so much for helping me in my digital logic exams! god bless you sir

[@mukesh_not_a_youtuber]

The explanation is too good.Thank you :)

[@GauravGupta-pb8mk]

Thank you sir

[@yuanshenchua7564]

So do we have to do state reduction?

[@rukmanpuri9787]

What about flipflop Which flipflop are you using??

[@thestrappingentrepreneur2822]

you are a godsend for my engineering program holy shit

[@ayadabdulkareem6456]

Thank you very much ... it can be reduced to 3 state... thank you again ...

[@dhanushdshekar4703]

state reduction was possible right?like s2=s3??

[@DebranjanPal]

Great, easily understandable, thanks.

[@rajshah2182]

Great video mate!

[@ravindraroyAIT]

i am confused with overlapping and non overlapping ..... please suggest me with eg such as 1101 , 11001,1010 how to draw state diagram

[@gyanig8501]

with hands holding a working pen and paper. Most imp, a tiny bit of thinking (if you have) ;)

[@ravindraroyAIT]

Dude some one replying after 4yrs seriously .....i am passed on but whatever thanks ☺

[@ravindraroyAIT]

But still dude you dont understand my question ....try some common sense haahaa

[@ravindraroyAIT]

And u still a nerd after all lol

[@Haroon13496]

thankyou sir..it was very helpful...Ur a great teacher..

[@deepanshmakkar5118]

Hat's off man

[@chandhrathejagannaram9047]

very nice lecture sir

[@arunsingaravadivelan3382]

I will not get the expected result if I design, sequential for the above state diagram. output y=Ax is the boolean expression we obtain, so it will not detect 3 or more consecutive 1's.

[@kaavyagowda4234]

Thank u..very useful video!!:)cleared many basic concepts

[@auvaisaraswathymurugesan1743]

extraordinary!!! very useful!! thank you for this video

[@deepakmanglani6954]

Please put the presentation no with the presentation as it is very confusing that which presentation comes after which. Please tell me which presentation order in which i should watch the videos after introduction to state tables.

[@NaolNaol-f5v]

thanks for all sir , but on the state diagram why the output is " 0 " when we go to s3 to s0??

[@vinayaksansiya]

please upload a video for sequence generator

[@ashutoshmoharir2474]

mealy can be written in 3 states only, moore needs 4

[@ashishkatakam861]

Plzz make a video on sequence generator also

[@DevarshiAggarwal]

life saving videos!

[@manojharshavardhan2385]

Is the State diagram for non overlapping condition.please reply thanks

[@d_simple9105]

Overlapping is confusing me. since more than three is mentioned ,so for non-overlapping case 1111 output is why 0?

[@engcuz]

Thnk you so much , It was very helpful in my Exam

[@devanggupta9986]

input can be any random set of the binary numbers....... please reply....

[@DEADY_Y]

Why we are not using a self-loop on s2 for 1/1,,, that would be easier without an extra state

[@dishantpatel287]

Sir....In this example...Whether you have considered overlapping or non overlapping?...I am very confused!

[@ayadabdulkareem6456]

over-Lapping ....

[@ShubhamBalsaraf]

Awesome..! Helped me a lot....

[@ShashiKumar-jv2cs]

sir, i have a doubt... why did u use negative edge triggering

[@juanpablotorres2143]

How much state i need used and how i now went the state go for other state (for the sequence ) ?

[@brycebanic6503]

Thank you for this video. You really helped me to understand.

[@fake_tourist]

So can we detect any sequence/pattern with this method?

[@ahmadsalmankhan3200]

Really great video.. It helped a lot.

[@tarannumkhan5943]

when input is 0, why it's going back to s0.. in previous example, when sequence doesn't match it's going back to itself... plz explain

[@nimrodmpandari7456]

Sir why did you put two states on your state asignment when you were detecting a 3 bit pattern why did you find the kmap for Qa+ n Qb+ n not for Qa n Qb

[@amentothatt]

s2 and s3 can be merged into 1 state.

[@riddhivekariya9086]

Doubt 12:15 why did he take Qa , xQb on k map rather x , QaQb

[@yashrajsonawane7734]

Bata deta bhai par teri exam ab ho chuki hogi jandee hard luck

[@shenoyshridhar]

plz do sequence generator also

[@usmanmukhtar8161]

Sir please tell me why the input is not given in questions relative to sequence detector ?????? & which input we select????

[@xiaoyangliu9261]

Thank you for making my life so much easier!!!

[@saumyagupta1632]

+Xiaoyang Liu sn't s3 an extra state what if from s2 i go to s2 for 1/1 and to s0 for 0/0 and there is no s3

[@RiteshKumar-go3do]

+Saumya Gupta Agree that

[@xyzw1850]

during state assignment, are we free to match any state to any set of bits ? I mean , what if i will say s2 as s3 and s3 as s2 ?

[@anuragmittal9816]

Please clarify : In Mealy model no of states = N , where N= no of bits in the sequence we want to detect ...here you wanted to detect 111 , ie n= 3 , but instead you took 4 states , why ????Please somebody clarify

[@mahnoorkhalid6496]

i have also the same question

[@nirajakinnal9435]

Can only 3 states (S0, S1, S2) be used in this case because when the 3rd 1 has to be detected, s2 state will be in s2 (1/1) and it will go to s0 for 0/0

[@fatizulfiqar]

really nice explanation.. but I just want to ask that how do we know that how many states are required for sequence detector..?

[@urdayz]

it depends on how many bit of the input sequence you want to detect

[@rajenderraj441]

how many minimum no. of ff required to detect any sequence using moore type detector for n bit...???

[@JoseRomero-wb3be]

The state assignment of S0 - S3, does it must follow the order you used in the video or can we assign them however we choose? For example, can I use S0 = 00, S1 = 01, S2 = 11, S3 = 10.

[@raj_rajput944]

You can name any state by yourself but for comfort we use it like binary for example S0 represent binary zero and similarly for all

[@sushantatudu870]

Why you used negative edge triggered clock?

[@narendrabogem5264]

Tq bro

[@srushtikotagi]

How could u consider input sequence

[@charlietokowitz]

your videos are so helpful!!! thank you!!

[@praveenkumar-hg4kz]

why didn't you use state reduction n why can't we stop it at state s2 is it necessary to do untill s3.bcoz it seems it works fine untill state s2 itself

[@anshulgupta2136]

please tell me why did you take an extra state s3......as the next state and output of s2 and s3 is same??

[@avinashtamilisetti914]

Why did u consider output values for realization

[@rajeevsimhadri8621]

Excellent

[@vinitvivek4574]

Hi sir, u have drawn this state machin by considering overlapping , wht is state machin if we consider non overlapping , the s3 sate must goes to s1 if i m not wrong , plss confirm

[@allaboutelectrical8763]

sir how u are taking s1 s2 and its values and how you u going forward

[@bun_zees3245]

What is the need for s3