Shift Register | SISO SIPO PISO and PIPO | KTU CST203 ECT203 ITT203 EET206 | Logic System Design

Syllabus Common to :
APJ ABDUL KALAM TECHNOLOGICAL UNIVERSITY (KTU)
(REGULATION 2019)
1)CST203 Logic System Design ( COMPUTER SCIENCE ENGINEERING)
2)ECT203 Logic Circuit Design (ELECTRONICS AND COMMUNICATION ENGINEERING)
3)EET206 Digital Electronics ( ELECTRICAL AND ELECTRONICS ENGINEERING)
4)ITT203 Logic System Design (INFORMATION TECHNOLOGY)
5)EBT205 Logic Circuit and Design (BIOMEDICAL ENGINEERING)
6)ICT203 Design of Logic Circuits (INSTRUMENTATION AND CONTROL ENGINEERING)
7)ECT203 Logic Circuit Design (APPLIED ELECTRONICS ENGINEERING)
(REGULATION 2015)
1)CS203 Switching Theory and Logic Design (COMPUTER SCIENCE ENGINEERING)
2)IT201 Logic System Design (INFORMATION TECHNOLOGY)
3)EC207 Logic Circuit Design (ELECTRONICS AND COMMUNICATION ENGINEERING)
4)EE204 Digital Electronics and Logic Design (ELECTRICAL AND ELECTRONICS ENGINEERING)
5)EC207 Logic Circuit Design (APPLIED ELECTRONICS ENGINEERING AND INSTRUMENTATION)
6)IC207 Design of Logic Circuit (BIOMEDICAL ENGINEERING)
COCHIN UNIVERSITY OF SCIENCE AND TECHNOLOGY
1) Master of Computer Applications (MCA)
20-381-0103 Digital Electronics and Computer Organization
2)EC-15-1304 Digital Electronics (BTECH ELECTRONICS AND COMMUNICATION ENGINEERING)
3)CS-14-1302 & 19-202-0302 Logic Design (BTECH COMPUTER SCIENCE ENGINEERING)
4)EE-15-1405 Digital Electronics ( ELECTRICAL AND ELECTRONICS ENGINEERING)
KERALA POLYTECHNIC DIPLOMA (SITTR KERALA)
1) 3042 DIGITAL ELECTRONICS ( DIPLOMA ELECTRONICS ENGINEERING)
2) 3042 DIGITAL ELECTRONICS ( DIPLOMA ELECTRONICS AND COMMUNICATION ENGINEERING)
ANNA UNIVERSITY ( REGULATION 2017)
1)EC8392 Digital Electronics (BE ELECTRONICS AND COMMUNICATION ENGINEERING)
2)EE8391 Digital Logic Circuits (BE ELECTRICAL AND ELECTRONICS ENGINEERING)
3)EE8351 Digital Logic Circuit (BE ELECTRONICS AND INSTRUMENTATION ENGINEERING)
4)CS8351 Digital Principles and System Design (BE COMPUTER SCIENCE ENGINEERING)
5)CS8351 Digital Principles and System Design (BE INFORMATION AND TECHNOLOGY)

[@letslearnelectronics8169]

Thank you sir all your classes are helpful

[@sijoa8204]

sir your teaching is very excellent easy to understand thanks

[@lofigirl676]

@23:15 siso positive edge triggering alle? but waveform clock pulse negative edge triggering aayitanallo varachekune

[@sneh_hh]

8:45

[@user-jl4wq2qn6s]

Really Great classes sir

[@nithyat9025]

Sir ,I have a doubt,timing diagram varakkumbo clk kazhinju Qa,Qb,Qc,Qd like this ee order il varakkamo

[@sijoa8204]

Varakyam

[@_z2397]

sir ithil timing diagram thettalle 9:13 karanam positive edge triggering varumpol alle active akullu sir varachathil negative edge triggering alle active akunne... please. verifiy

[@ShastraTechnicalInstitute]

Negative Edge Triggering Method is most widely used ! Clock will activate only if Falling Edge Occurs

[@sana.snavas5172]

Negative clock pole ano positive clickintem@shastra technical institute

[@aryasreekumard6552]

Thank you so much sir .

[@dennaaj8532]

AWSome classes sir❤️❤️

[@Helen64]

2019 scheme il piso pipo indoo..please replyy

[@anandmohan5538]

Super class

[@nixongeorge7999]

Superb class

[@appu2871]

Thanks a lot sir 😻

[@Rahul-jk7es]

Life saver

[@murielleosias5018]

Hello Sir, Can You Please Upload Classes Related to PLA, Rom Etc.. M

[@ShastraTechnicalInstitute]

Sure !

[@learnece9538]

kzbin.info/www/bejne/i3mrmoWuptp0jqs

[@rockstreethomie]

Do right and left really matters?

[@mitul22br]

Sir SISO de waveform negative edge triggering based anello vannekkunnath. Theoryil positive edge triggering aanu paranjathu

[@sana.snavas5172]

Thank you sir😇

[@Abhiram-gx8si]

എന്റെ സാറേ 😻

[@bhavyar6778]

Sir notes??

[@rayeesashihas1332]

Great sir😍

[@aiswaryaanil8679]

Thank u sir

[@ShastraTechnicalInstitute]

Most welcome!❤❤

[@ashmi1237]

Sir, verilog nte videos cheyyumoo??

[@ShastraTechnicalInstitute]

Yes Cheyyunnundu ! Will be uploaded after Jan 10th

[@ashmi1237]

@@ShastraTechnicalInstitute thank you sir

[@learnece9538]

kzbin.info/www/bejne/i3mrmoWuptp0jqs

[@Lobster.Gaming]

Sir full adder and subtracter universal gate vechu chayuna video idummo....it would be really helpful 😊

[@mithrabinu950]

Sir SIPO 3 Flip-flop vech varachal tett ano ...

[@ansara7952]

Hello sir,can you please uploade classes Ece Minior subject analog communication & please create a playlist for that subject

[@ShastraTechnicalInstitute]

Okay I will try

[@learnece9538]

kzbin.info/www/bejne/i3mrmoWuptp0jqs

[@chaithanyaraghav9319]

*Logic circuit design Sample Question paper (EC) plzzz 🙏🙏🙏🙏🙏🙏it would be very helpful for students like me 🙏🙏🙏🙏* 🙂🙂🙂

[@fathimanubla975]

Sir syllabusl piso pipo illalo appo ath xam nn chodikn chance undo???

[@ShastraTechnicalInstitute]

PISO PIPO koode padikkanam

[@aswinjayaji3127]

2019 schemenu piso pipo undo ?? athu padikkano

[@sijo3751]

Yes

[@hennamaria8967]

But ktu syllabus il ella lo 😑

[@Helen64]

samedoubt here

[@naachuuu8865]

Sir, sirinte notes evda available?

[@jasimihsan2912]

Thanks..

[@crv2706]

സാർ ഇതിന്റെ നോട്ട് തരുമോ ഉണ്ടങ്കിൽ

[@ShastraTechnicalInstitute]

Ready aayitt ayakkam

[@brtkid3553]

@CRV note thramo

[@sulochanag7750]

Sir ithinte notes tharamoo

[@greeshmanp7589]

Thank u sir