Single-Cycle Timed Loops in LabVIEW FPGA

[@luisramongrandecastillo2084]

Great video. BUT... why if you dont explicit way you want one clock cycle, it takes 7 ticks in this example?

[@christiant.9039]

Guess it simply depends on synthesis of the FPGA. When using "default" loops, the configuration on the FPGA is done in a way to minimize resources while keeping good execution times. When forcing it to execute it within one clock cycle, it should use more resources of the FPGA since faster execution times always correlate with either higher clock speed (which is not the case obviously) or parallel execution (Compute in Space).

[@honorbean2973]

Thanks for the video, I learned to use VHDL or Verilog instead.

[@neobuddy2010]

The Audio is Broken. Please Fix if Possible.

[@JamFlexx]

bruh I can't stand this program .

[@ГеоргийБычков-с7о]

Nothing usefull...