Standard Cell | Standard Cell Layout | Standard Cell Library | Tracks of Standard cells

[@debmallik]

hi good job...can you explain how to calculate width of VDD/VSS for different tracks standard cell library(7T/10T/12T)

[@jahnuchoudhury6677]

Thank you Sir .. very helpful ..

[@TeamVLSI]

Thanks a lot jahnu. Keep supporting.

[@arkanjo7509]

Thanks

[@TeamVLSI]

Welcome Arkanjo!

[@venkateshsanagala8287]

Sir can you upload matching techniques in layout,types of matching,why matching is required

[@TeamVLSI]

Hi Venkatesh I have not explored the said topic too much.

[@14-ds-nagamanicholleti60]

Good explanation sir👏👏. sir Are you having any standard cell library with you which includes AOI and OAI gates. Can you please send me sir.. Please.

[@DD-sm2gz]

Thanks a lot.

[@TeamVLSI]

Most welcome dear!

[@damarlaparadhasaradhi9617]

For example, I am doing PnR using ICC2/Innovus tool. so how do i know which no.of track SC library i am using? So generally how to check which track SC lib using?

[@TeamVLSI]

Hi Damarla, There might be more simplest way to find it, but one simplest way you can do, find the height of standard cell and find the M1 pitch. and (cell height) / (M1 pitch ) will give you the tracks in standard cells.

[@damarlaparadhasaradhi9617]

@@TeamVLSI Thank you

[@shahidafridi90]

Well explained Sir !

[@TeamVLSI]

Thanks @Shahid!! Keep watching...

[@rajeshraj5547]

Hi sir You said that more width means more height How both are related In our standard cell library height is fixed but having different widths

[@TeamVLSI]

Hi Rajesh, Could you please point me the timestamp so I can check it again.

[@aparnagupta3872]

Hello sir, Why did you divide by 190nm to get the no of tracks?

[@TeamVLSI]

Hi @Aparna I am not getting your question clearly. Can you mention the time stamp, so I could check and reply to you correctly.

[@RamakrishnaV447]

M1 metal pitch is 190nm , To get no of tracks for total height (2470nm) of stdcell we need to divide by pitch

[@aparnagupta3872]

@Rama Krishna, thanks for replying.. Why M1 pitch is taken in the picture and not some other metal layer?

[@habibakhatunnesaragi6259]

very nicely explained sir amazing .......

[@TeamVLSI]

Thank you Habiba!

[@ArunChikkaraju]

I have one doubt You have said that the std cell height should be fixed and width can be varied but in 27:42 we have cells with various heights can anyone explain about this scenario?

[@谷夫琅禾费]

That's because they are three sets of std cell. They are placed there to demonstrate that the std cell could have different kinds of height, but in one SoC or circuit layout only exists one kind of std cell height.

[@mohangowda4282]

hi sir , In few of std cell design . m0 vss/vcc pins are left dangling for top connection . and are hooked to top power without using tie cells ...why this is needed

[@TeamVLSI]

Sorry, i have not encountered such cases in my experience. Could you please give more descriptions on this?