Strange way to blink an LED: Demonstrating Clock Hardware IP Blocks on the Tang Nano 9K FPGA board

[@spillagonner]

Greg...at 7:16, after having done the floor planning, you say 'and...we should be able to synthesize...,' when you mean to say 'place and route.'

[@electronics.tinker]

You are right. I had not noticed that misspeaking. Cheers.

[@ErikS-]

Excellent tutorial.

[@durka8892]

Hello, I'm new to the world of FPGAs, and I have a question. The TangNano 9K has a 27 MHz crystal oscillator, but I can generate a higher clock using the PLL. My question is: what is the maximum frequency I can achieve? At 2:05 in the video, a table shows 1200 MHz-is that correct? But at 0:55, it mentions a 200 MHz clock. I'm a bit confused about this part. Thank you for the video.

[@electronics.tinker]

It's a good question. In general, you have to dig through and understand technical documentation available on the Gowin website to answer this type of question. The FPGA on the 9K is a GW1NR-9 with speed (and temperature) grade C6/I5. I am looking at document "GW1NR series of FPGA Products Data Sheet", version DS117-3.0E. Its Table 3-21 answers the question saying the max valid CLKOUT from rPLL is 600 MHz (and the min is 3.125 MHz). The table also gives limits on intermediate clocks that are involved. A separate document "Gowin Clock User Guide UG286" explains those intermediate clocks and how they form CLKCOUT. It's not easy stuff, and there are many docs to shift though. And then, you need a design that can actually use a 600 MHz clock while still meeting setup and hold times. I doubt there is much you can do on the GW1NR at such a high speed. It's why you have to look at the timing report that the tools generate to see if your design meets timing. There are still many aspects of this that I cannot understand from Gowin's docs. But I know that red text in the timing report means "bad!" Good luck with you FPGA.

[@stephanbrenner3317]

thanks for this great video. May I ask whether you have figured out how serious are the limits of rPLL? I'm interested in the lowest possible input frequency of the PFD. It is given with 3MHz. Does it work below or not? Many thanks.

[@electronics.tinker]

I did not try to test the rPLL out of specification. And it might be hard to do this test. I think the Gowin tools check that IDIV_SEL, FBDIV_SEL, and ODIV_SEL are valid so builds may fail if you edit the generated Verilog to substitute out of spec values.

[@simoneden3665]

I wonder, if using this method utilises less silicon overall compared to blinking an LED with something like an Arduino.

[@electronics.tinker]

My guess is that the GW1NR-LV9 used on the Tang Nano 9K is larger in silicon area than a small Arduino (ATmega328). But most of GW1NR-LV9 is not used to blink the LED. Maybe the very smallest sort of FPGA could give an Arduino a run for its money in blinking an LED. But much smaller microcontrollers exist also. They likely win the prize. The flexibility of FPGAs can cost 10x in area versus a dedicated design.