Structural Hazards (Hazards in Pipeling)

[@saadqayyum2148]

First: it should be SUB R1, R8 at 4th clock cycle for 3rd instruction. Second: its a Read after write data hazard. For a structural hazard, you should swap the order of 1st and 3rd insructions. Correct me if I am wrong

[@saikirananumalla7226]

Thanks for the Very clear explanation on pipelining and hazards , thank you ma'am

[@rintusamanta9480]

mam i want to say yoy that, in the clock pulse for 4,...and for ID,,,there have sub not add

[@chinnikrishna8178]

Thanks,its very good, easy to understand the concenpt

[@sainarendra2325]

One question, as far I know this comes under data hazard, as we are trying to write and read from the same register, isn't it called Direct Register Data Hazard?? Correct me if I'm wrong. And I think a memory location from where we are trying to fetch the instructions (clearly not data but the entity which converts as instruction opcode) and if we try to write back data in to the same location causes the structural hazard. it can resolved by maintaining separate I-cache and D-cache.

[@AbhayAgrawaluploads]

Appreciate ur efforts.. u r doing a good work mam...Keep posting lot's of questions series too.. That would be helpful for Gate aspirant s

[@ritukapurclasses1591]

Thank you... Means a lot...

[@AkhileshPandey-bv5ni]

Appreciate your efforts Maam, But I think for the clock pulse 4 the respective ID phase should be SUB R1,R8; Anyways this series was good, very thoughtful. Cheers!

[@lathas9701]

Same doubt...clock pulse 4... should be sub r1.and r8

[@sabinalefebvre6567]

very good explanation thanks a lot

[@ritukapurclasses1591]

Glad you liked it :)

[@arnavraj4293]

ma'am your voice is soo soothing that i can't stop myself to comment.. thanks for making me understand

[@ritukapurclasses1591]

Thank you..

[@waltercordero2176]

could you provide the previous videos that you mentioned during this video?

[@mohammadinshaulhaque6330]

mam, how data hazard is different from structural hazard?

[@hiraimran377]

Is may jho red marker sy circle ha Wooh add ka operation kasy ha. Overall good effort.

[@abhishekanand9109]

This example is just like *read after write * hazard

[@30benasabu65]

madam so when the conflict occur at same clock pilse it become structural hazard if its not then it become a data hazard is it correct

[@MahEsh-jf7uu]

Mam In diagram.In Instruction decode 4 th clock it may be SUB not ADD rigth ?

[@ritukapurclasses1591]

Yes you are right... Thanks for pointing it out

[@subhadippatra7930]

What is pipeline latch latency?

[@syedzada7011]

You have not discussed about the memory pulse as there are five pulses to complete one instruction as Instruction Fetch instruction Decode Execute Memory Write back

[@siddhantdutta7427]

mam what if we do it by operand forward technique??? in that case there will be no loss/wastage of clock cycle. will that answer be right??

[@ritukapurclasses1591]

Yes, we can definitely use operand forwarding technique as well. So, my main focus here was to explain d concept of Structural hazard. But both the answers will be correct.

[@siddhantdutta7427]

@@ritukapurclasses1591 oka mam. I got what you said. Thankyou

[@ehtashamulhaq3723]

thanks Mam

[@kashmiriplanet9917]

StiLL confused mam...😥😥