Synthesis/STA SDC constraints - Create clock and generated clock constraints

[@merrygo7189]

Good explanation sir... Keep it up... I will share your videoes in my VLSI grp

[@VLSI-learnings]

Thank you

[@sarathc1456]

Please give me VLSI group link

[@c.nagasurendrababu156]

I saw your all videos very nice explanation Bro

[@VLSI-learnings]

Thank you

[@muthukumaranm9281]

Nice one. Put more videos on writing STA constraints

[@VLSI-learnings]

thank you

[@Rcs9060]

very nice explanation sir

[@VLSI-learnings]

Thank you

[@AB-od7ug]

Very nice Explaination👍👍

[@VLSI-learnings]

Thank you

[@umavathimarichetty2050]

Very nice explanation sir..

[@VLSI-learnings]

Thanks and welcome

[@rm997]

how can the worst negative slack obtained from vivado be used for determine the critical path

[@tejalpawar7199]

Sir suppose my digital design works on 2 external clocks say clk1 and clk2 . These two clocks have same time period but they are non-overlapping clocks. How to write constraints for these clocks and how to give input and output delays with respect to these clocks?

[@VLSI-learnings]

we will use false path bitween those to clock or we have to use set max delay constraint

[@petsanimalsshorts6200]

If from PLL generated clock is there, then is it nessary to add false path for input clock and output clock?

[@VLSI-learnings]

PLL will generate clock for all block.. you have to write create clock Constant for particular clock

[@shivamshrivastava1794]

Hello Sir, what actually "x" and "y" represent here?

[@Shahidsoc]

Hello, if reference clock is coming to pad then to pll whcih generates 100 times more frequency signal dco_clk_o(0) and cl_p_acc then to digital_top at clk_h pin and then goes to clock gates module clk_rst_asic_gen_i_clock_reset. How to constraint it ?. Clock gate module then generate multiple clocks. clk_p_cpu, clk_p_cpu_n, clk_e, clp_p_acc etc. I tried following, but in qor report shows no path . Kindly guide. create_clock -name "PLL_REF_CLK" -period 40.0 -waveform {0.0 20.0} [get_ports pll_ref_clk] create_generated_clock -name "DCO_PLL_CLK" -multiply_by 100 -source [get_ports pll_ref_clk] [get_pins {i_pll/dco_clk_o[0]}] create_generated_clock -name "CLK_P_ACC" -multiply_by 1 -add -master_clock DCO_PLL_CLK -source [get_pins {i_pll/dco_clk_o[0]}] [get_pins i_digital_top/clk_p_acc] create_generated_clock -name "CLK_H" -multiply_by 1 -add -master_clock DCO_PLL_CLK -source [get_pins {i_pll/dco_clk_o[0]}] [get_pins i_digital_top/hclk] create_generated_clock -name "CLK_P_CPU" -multiply_by 1 -add -master_clock CLK_H -source [get_pins {i_digital_top/hclk}] [get_pins i_digital_top/clk_rst_asic_gen_i_clock_reset/clk_p_cpu] create_generated_clock -name "CLK_P_CPU_N" -multiply_by 1 -add -master_clock CLK_H -invert -source [get_pins {i_digital_top/hclk}] [get_pins i_digital_top/clk_rst_asic_gen_i_clock_reset/clk_p_cpu_n] create_generated_clock -name "CLK_E" -multiply_by 1 -add -master_clock CLK_H -source [get_pins {i_digital_top/hclk}] [get_pins i_digital_top/clk_rst_asic_gen_i_clock_reset/clk_e] create_generated_clock -name "CLK_P_ACC_INT" -multiply_by 1 -add -master_clock CLK_H -source [get_pins {i_digital_top/hclk}] [get_pins i_digital_top/clk_rst_asic_gen_i_clock_reset/clk_p_acc]

[@nephewniece3312]

Hi, what are the area constraints??

[@VLSI-learnings]

area report constrains i will not explain here .

[@Shareefsmtg]

sir waveform taken by 2 of clock period sir

[@MusicalVibes711]

Sir how do we decide what should be the clock period. How do. Decide frequency and time period

[@VLSI-learnings]

clock frequency decided by the customer. We have to design as per that frequency

[@akashwayal8797]

sir in which field you are working? just asking.. please make more videos !!

[@VLSI-learnings]

Sure .i will do

[@VLSI-learnings]

Sure .i will do

[@raviram8954]

Why should we create generated clk

[@reshmas3714]

Thankyou sir

[@VLSI-learnings]

welcome

[@merrygo7189]

Sir if you get time then make a video realted to SDC constraint ...what are the challenges we face during SDC settings in a real life project .... because for a block owner we get SDC frm fcfp only ..

[@VLSI-learnings]

sure

[@prajwalmali8054]

500mhz how you get 2ns

[@mnithish]

Can you continue your knowledge sharing... Why 🤔 you stop...?