System Architecture: 7 - Accessing PCIe Config Registers

[@pavandn]

Excellent explanation. I was trying to dig through so many books and info but was unable to get the exact info I needed. But your videos provided most of the info I needed.

[@lejnyovn9251]

Great videos, Most valuable Informations, these are the "MISSING LINKS" of the "BIG PICTURE" . Great work, expecting more videos, THANK YOU SO MUCH.

[@neerajvishwakarma9021]

Very good explanation to understand the basics of config space handling in PCIe

[@ΝικόλαοςΜελάς-π2γ]

Nice and clear explanations from an excellent engineer. Thank you :-)

[@Mr_ST_720]

Thanks so much sir from Maharashtra

[@chandrasekharanumula4137]

Hi sir, why we need to write into 0xCF8 and read from 0xCFC ? Why can't read and write from the same register? Thanks, Chandra

[@vivekvilvaraj1457]

0xCF8 is the CONFIG space address you need to access, and 0xCFC will have the data from that address

[@mdmuazzamhusain6839]

Please keep educating us

[@nagarajkumarnarayanan9179]

Thanks a lot for your explanation

[@lorddiaboboss]

Wow, very nice but over my for execution. How do I fix when 2 of 8 GPUs properties Bus is 9 and A. My z270 chipset motherboard has only 7 PCIe plus one m.2 configured to PCIe and one for x4sata.

[@EvilSapphireR]

How does the port mapped I/O requests (via the In/OUT instructions) reach the PCI config registers in the first place? Do the motherboard vendor solder the buses coming out of the CPU into the system agent in such a way that this would always be the case (possibly following the PCI/PCIe specification?) ?

[@yoav_1867]

how are you doing, I remember you from the OST1 OG class. might be a lil too late to answer. Anyways, I asked the same question when I learned this and these are the conclusions I came up with: on a x86 system, the system itself is built on a pci "backbone". so every access to peripheral is done via pci communication first, whether directly communicating to a pci device or regular device (via a controller which is just a piece of hardware in the pch that knows how to communicates with the bus interface etc. but is ultimately pci function or really just a pci device itself). so with that in mind, there should be a pci bus protocol to communicate with everything on the system because everything is built on pci/e device chain. so what actually happens is when the system agent gets a request from the cpu to talk to a peripheral it creates a pci transaction (which is part of the protocol). if you look up the pcie transaction types you will see MMIO R/W transaction, Port IO R/W transaction, but more importantly Configuration W/R transaction. so I think what happens is when the system agent gets a port IO requests but with CFC and CF8 ports for configurations it just creates configuration transactions which the devices can understand (they built that way) instead of regular port IO transactions.

[@alokcom]

Once Enumeration is Done where B:D:F information stored?

[@CD-dm7sf]

I think it is maintained in the device data structure in the low level firmware code that does the enumeration e.g. in OS device driver's data structure. The driver initializes one structure per device and uses it to read/write to the device

[@alokcom]

Hi Sarathy , First of all Thanks for wonderful series on system arch....have few basics query...Where are actually PCIe Config space registers are present , In Root Complex or Physical RAM or PCI Device? Who does the PCI enumeration BIOS or OS? How is DMA mappings done by PCI...?

[@sarathyj]

Config Space registers are present in PCIe devices (they can be root ports, switch ports, or end-point devices)

[@nagarajn5052]

AFAIK: PCIe registers are in the PCIe device. For ex. if it is a GPU device then those registers will be in GPU. BIOS does enumeration. Typically the devices come up even before OS has booted up and drivers have loaded. Question on DMA mappings --- no idea.

[@المبرمج-د3ر]

شكرا لك

[@tanyagupta3034]

Since config registers are DW aligned, then why do we need 8 bits for accessing 256 Bytes ? shouldn't we need 6 bits since 256 bytes are 64DWs.

[@sarathyj]

You can have byte access for PCIe config space registers. For example, Primary/Secondary/Subordinate bus number registers are all byte wide. So, you need 8 bits for accessing 256 bytes.

[@sivalakshmiperam2798]

Hi Sir, Your video is really helpful in understanding pci config registers. Thank you so much. Here i have one doubt. In config space registers for address CF8 MSB bit i.e., 31 bit is 1. Can you please help me in understanding about this en bit. i.e., what happens if we make this bit 0/1. Thank you in advance

[@prabhu1970]

Even I need this explanation please clarify

[@MrRamsampath]

nice.video is mot clear .ca you please host again