System modeling of Processor Pipeline using VisualSim Architect- RISC-V and ARM Cortex A77

Purpose of this Video and the VisualSim Microarchitecture
Designing a processor at cycle accurate level requires detailed specifications about the instruction set architecture and the hardware components. VisualSim provides the ability to design and analyze both the ISA and the internal hardware devices.
Users can utilize the existing ISA or design their own ISA for a custom processor. With VisualSim, the user can determine the behavior and usage of each instruction that can be processed by the pipeline stages. Designing a high-performance processor requires recursive analysis to select the optimal configuration. VisualSim provides the hardware libraries for pipeline stages, interconnects, and memory devices, that can be configured as per the design specification. Based on the simulation results, the user can fine-tune the configuration to improve the system's performance.
Analysis that can be done using this library
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For a processor design, the designer wishes to analyze the CPI of the implemented hardware for a specific workload. VisualSim provides detailed performance statistics and debugging information to analyze and optimize the system. The key statistics include the CPI, Memory access latency, Total number of instructions executed, and the total number of instructions committed. Designers can also observe the utilization and occupancy of the resources to improve the hardware design. Apart from the performance analysis, VisualSim provides the ability to analyze the power consumption of each device as well as the entire system.
Differences between Hybrid and Microarchitecture Modeling
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VisualSim has a Hybrid processor and Microarchitecture design library. Both are used for emulating the processor, but each has its own purpose and advantages.
The hybrid processor library performs trace-based execution while the microarchitecture library performs dynamic scheduling, actual instruction execution, and, branch flow handling within the pipeline stages. The hybrid processor will be beneficial for someone who wishes to analyze the devices and operations that are external to the processor. Such as memory access performance, DMA operation, IO accessing, and interconnect performance. The microarchitecture library focuses on the detailed analysis and improvements of the internal processor design along with the external hardware. With this, the designer can observe the actual values being read or written in the registers and memories. The Instructions that are being processed and propagated through each pipeline stage can be observed. They can also observe the actual behavior of each pipeline stage through the execution like buffer occupancy, stalling, flushing, resource utilization and etc.
Model Demonstration:
The video shows the architecture view of the Arm cortex A77 processor.
Model Simulation
We can observe the final CPI of the entire run as 3.59 and the total number of instructions committed is around 45K. The number of instructions executed shows the instructions that are executed speculatively. We can also observe the total micro-ops scheduled and the number of macro instructions converted to micro-ops.
The user can also observe the number of instructions executed in each functional unit and the average utilization of each unit.
One of the important features of VisualSim is the power analysis, we can see the power plot that shows the instantaneous and average power consumption for the entire design over the simulation.
Along with this, users can observe the executed trace of the source code and the final values updated in the register.
During the simulation, we can observe the performance of the pipeline by checking the Average CPI. It describes the time period where the performance is getting increased or decreasing.
The memory hierarchy plays an important role in processor design, and that can be analyzed through the statistics generated over the simulation.
Such as the hit/ miss ratio of cache, throughput, writebacks, eviction, and utilization. Similarly, we can observe the statistics for DRAM and interconnect devices.
Apart from the analysis, the microarchitecture library support debug features to validate the internal functionality of each pipeline stage. This can be enabled by selecting the debug enable option.
Users can observe the actual execution of each instruction to validate the correctness of ISA by enabling the behavior debugging option.
RISCV model
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We support separate libraries to model the RISC V architecture. The user can observe a similar configuration and analysis structure. The key difference is the internal logic is implemented according to the RISC V architecture.