Systemverilog Callback With Examples

[@rupankardas8241]

Hi. Its a wonderfull explaination. Can you please provide the EDA link.

[@ParthVikani]

Jast curious to know more about you... If u can share linkedin profile

[@SystemverilogAcademy]

www.linkedin.com/in/ajith-jose-88502735/ :)

[@ganauvm270]

hai can make a paid tutorial for RAL?

[@SystemverilogAcademy]

Thanks for the suggestion, it's already on my TODO list. Will try to do, but may not happen in few month.

[@sherinelias5197]

Hi sir can u explain dual port ram

[@SystemverilogAcademy]

Hi Sherin, sorry I don't think I can help you here.

[@ganauvm270]

really good. can you explain solve before constraint

[@SystemverilogAcademy]

Thanks. In simple words, 'solve before ' is used to specify the order in which constrains has to be evaluated, if needed. But don't assume they are used to specify the ordering, in fact they just change the probability of occurrence. Eg: class my_class; rand bit en; rand bit [7:0] bus; constraint c_bus { !en -> bus == 0; } constraint c_order { solve en before bus; } endclass: my class Even if the constant c_order was not present, bus will be always 0 when en=0. But in that case, the probably for en=0 will be just 1/(1+ 2^7), but when the constant c_order is added, it will jump ti 1/2. For a bit more detailed explanation, you can refer the LRM section "Variable ordering" under "Constraint Random".