Latch and Flip Flops in ASIC Design

[@priyasahoo4280]

Thank you for the wonderful explanation over this topic. I have one query, as we know latches are level triggered so more prone to glitches. Then in high frequency ASIC why latches are used?

[@mukeshkumar-hx9tl]

In High frequency latches are used to fix setup, as time borrowing concepts in sta .

[@TeamVLSI]

Hi Priya, Good question. Answer is latches are helpful to meet to timings, How It helps, I have answered in other videos... And here I want to investigate this part of question by yourself.

[@mukeshkumar-hx9tl]

Thank you sir and team VLSI for tutorial videos I have some questions but I don't it valid que or not. Is Latch have rest pin ?, if no then why we are not add reset pin and if latch have reset pin then what about reset assertion and reset de-assertion in design.

[@TeamVLSI]

Hi Mukesh, We have only D, Q and EN (or CLK) pins for latch.

[@mukeshkumar-hx9tl]

@@TeamVLSI thank you sir

[@pkb28]

Which one is best Latch or Flip flop?

[@TeamVLSI]

Hi, There is no straight forward answer of this question. Both has it's own importance.

[@sairamsmart2779]

Is there any active whatsapp or Telegram group link?

[@TeamVLSI]

Yes, please join. chat.whatsapp.com/HzCxJjtXgLP9j13R7m5HHq

[@bijjulapruthwi9954]

Can't join the WhatsApp group, since the group is full

[@TeamVLSI]

Sure Bijjula, You can join our new group through following link. chat.whatsapp.com/C2B7VjYwCicFLenxg8cf1i