That was brilliant, and answers the questions in my mind before even asking (about using multiple accelerators). Thank you guys
@SperlingMediaGroup Жыл бұрын
Glad it was helpful!
@echindaplatypus2 жыл бұрын
Fantastic video, thanks for all your hard work Ed.
@aliuzel42113 жыл бұрын
Great video. Thank you.
@samc63682 жыл бұрын
Nice short tutorial ! I used to work few cubes from Gary at G*, he always explains simplified at any level. Thanks Gary.
@SperlingMediaGroup2 жыл бұрын
Glad it was helpful!
@Alorand5 жыл бұрын
What I would like to know is if this standard could help multiple GPUs share a workload in a scalable and low latency way that would improve on what is possible with SLI or Crossfire.
@surajby80895 жыл бұрын
Have some queries: 1. How does CXL achieve low latency? Is it by introducing the device biases and multiplexing three different sub protocols? 2. What do you mean by dis-aggregation? How does CXL solve this problem?
@sumankumarpatra71154 жыл бұрын
1. Low latency: In comparison to the existing cache/mem protocols PCIe link is much faster 2. Dis-aggregation of the workload from CPU to accelerators
@alexisfrjp2 жыл бұрын
There is nothing special for low latency in the protocol, it's just the way you access data. For a DMA operation, instead of reading the DDR, you read the cache that has a lower read latency. It's a fake low latency characteristic.
@siddhiL-sd6ru6 ай бұрын
thanks
@chethanm53555 жыл бұрын
we can achieve Gen1 --> Gen3 speed without going to Gen5 in CXL ?
@sumankumarpatra71154 жыл бұрын
Yes...But it will, in application, defeat the purpose of high bandwidth
@chethanm53555 жыл бұрын
one query? CXL support Gen4 device ?
@sumankumarpatra71154 жыл бұрын
Yes. Gen3 and above
@anupganesh27674 жыл бұрын
@@sumankumarpatra7115 : Native Gen3 device or it has to be Gen5 degraded to Gen3 ?
@vinayt71594 жыл бұрын
How to know full concept of CXL
@vinayt71594 жыл бұрын
Please suggest any one
@SperlingMediaGroup4 жыл бұрын
Here are some additional resources in Semiconductor Engineering's Knowledge Center semiengineering.com/knowledge_centers/standards-laws/standards/compute-express-link-cxl/