Transistor-9 - Substrate and Gate Leakage

[@Amansingh-nl4ev]

@9:00 does pn junction have leakage current during Forward biasing?

[@bharadwaj767]

02::07_09-04-24_@IIIT-H substrate forward bias --> current flow & transistor scaling leads to Gate tunneling (low oxide thickness)

[@mohdaarifanwar2471]

13:42 increasing the thickness capacitance goes up???/

[@swfs253]

For gate leakage when you said 180 nm 130 nm 45 nm etc did you mean oxide thickness or distance between drain and source?

[@AbhishekSingh-up4rv]

drain and source dis

[@vivekartist6893]

He was refering to the process node. It has nothing to do with the physical parameters like oxide thickness or channel length but its related to manufacturing process. Over nodes lowering, the dimensions of transistors reduced, thus accommodating higher number of them in a chip.

[@muhammadhamzashahid9649]

Excellent.

[@monkinght6980]

Sir it's not clear whether you telling about gate length or tox thickness

[@monkinght6980]

11:19 here

[@abhayh924]

@@monkinght6980 Neither. its just a technology parameter referring to the size of the transistor in its entirety