TT02 ASIC/board: Open source silicon chips on Tiny Tapeout! sky130 VLSI design getting started cheap

[@BeefIngot]

Its crazy the amount of technologies previously only accessible to engineers working at large companies that are increasingly availible to common people. Feels like there isnt enough time in the universe to learn even the basics of all of them.

[@fooglestuff]

There really is too much to learn, but it's pretty exciting to be able to go so deep in so many interesting areas of this industry now. And yes, it blew my mind when I started to realise what I was getting into about a year ago... where will it be in another year?

[@xeroname]

What a amazing project! Hopefully keep it going and thanks to the distributors working on these kind of projects!

[@fooglestuff]

I should point out that this is not sponsored... I just believe in the project, I think it needs more exposure, and I think it's pretty cool for anyone to be able to be involved :) Looking forward to more cool designs to come out of this and push the envelope further.

[@root42]

TT is intriguing. I wonder if at some point people will reproduce vintage chip designs. The retro community is using FPGAs for that at the moment, but something like TT would be interesting and maybe even cheaper. Many designs would require significant amounts of transistors though.

[@ArneChristianRosenfeldt]

If this chip only runs 20 MHz , vintage means .. uh our ET3000 had 50 MHz DAC. 286 of a friend had 20 MHz. Can’t even PSX. 3do maybe? Amiga 600 ? C64 superCPU has 20 MHz. The intro looks like TT should use variable size partitions. I still don’t get how this can be slower than FPGA. Inspired by Jaguar and Amiga, I would love to see that you could define a pattern in which chips can fire an write to a common 64 bit bus. Everyone listens. I like how Rambus brought transmission lines to the masses. Maybe the bus could actually be linear and meander over the chip and we compensate timing skew? Balanced signal and sense amps. Circuits far from each other don’t hear each other. Signal is damped before a round trip.

[@fooglestuff]

I find this intriguing too. There are successful and in-progress projects for recreating retro systems/parts already, and it's a fun challenge: TT04/05/06 provide 26 digital pins (with some caveats); fewer than normally required for much retro hardware. The upside is a much faster clock and higher transistor density than you'd find in the 1980s and early 90s. This has led to some clever reimagining of interfaces such as using SPI or muxed buses, or even putting more of a total system in a single design (kind of like an SoC). I expect this will only get better with time.

[@fooglestuff]

The area-sharing design is different for TT04 and above and expected to be better, but expected characteristics haven't formally been released. While *internal* clock speed could theoretically be well in excess of 100MHz, indicative figures are that inputs would max out at 66MHz, and outputs at 33MHz, but maybe closer to 28MHz. These limits exist because of characteristics of the IO pad circuitry (within the Efabless "Caravel" padframe), with extra load/delays because of the internal mux between all designs. As more info becomes available, I will endeavour to share :)

[@ArneChristianRosenfeldt]

@@fooglestuff so I read that mixed digital analog is coming. Still I prefer pulse mode width output (plus carry) from a tile directly adjacent to the pad for video output. VGA RGB needs 20 MHz. Even a slow pad should be able to reproduce an edge without jitter or at least output low pass filtered analog. I liked the shift towards sending audio via SPI to a DAC to minimise the number of traces which could send noise into the DAC. Controller input also better is serial. Yeah, I mean system of a chip, only that everyone could mix and match. So there would be the most most popular CPUs and the most popular GPUs . I just want each of them to be able at clocks higher than the 200 of the FPGA. At least FPGA is available to the masses, while TT seems to be under legal obligations to only produce enough samples for university students around the world.

[@root42]

@@ArneChristianRosenfeldtoh, I am thinking REAL vintage. Like 1MHz 6502 style... sure the faster parts will be out of reach still and many will require too many transistors. But it's a start...

[@DeltaEngineer]

wow what a gem of a channel, the quality and presentation are excellet. I was surprised when I scrolled down and it is not thousands of subscribers. Keep up the good work!

[@fooglestuff]

Thanks @DeltaEngineer! I really appreciate the feedback. Learning the open source VLSI design process has dominated my last year but I think now it’s time to get back into videos and there’s plenty of fascinating topics in this new domain!

[@tommythorn]

Really excellent presentation of the demo board and some of the designs. I hope you'll do more of these (I have a design on TT05).

[@fooglestuff]

Thanks Tommy! I definitely will do more, and maybe look at some specific designs in more depth, particularly as they now can be more sophisticated and much faster. Feel free to share a link to your design, if you like.

[@vicktorioalhakim3666]

Great video and channel! It's amazing how VLSI and ASIC design is finally getting more democratized and open to anyone. Back at grad school we were forced to use these overpriced (and shitty) tools (Synopsis, Cadence, etc) to finish our coursework on SoC design and such, and it was a great pain. The licenses were locked to a few computers, which meant that we had to take turns to finish the design, test and verify. Taping out was out of the question, but with this the game is slowly changing. I hope such opensource tools like Tiny Tapeout leak into the usual IC design curriculum around the world.

[@fooglestuff]

My apologies for the late reply, but thank you so much! The younger version of me never thought I'd be lucky enough to get a chip manufactured, but now it's happening :) One aim with projects like this is to attract hobbyists, beginners, and future advocates... but also encourage more professionals from other domains (especially software developers) to learn the process, and I think it's working... the open source tools are starting to reach some good points of stability, and the newer features offered by Tiny Tapeout and an upcoming new revision of Caravel (by Efabless) are starting to get pretty interesting, especially with growing attention to analog and mixed-signal designs.

[@pieterboots8566]

Multiplexing some internal memory would be a nice addition.

[@fooglestuff]

Agreed! There have been experiments with small amounts of on-chip SRAM (on the order of 1KiB) in some of the TT shuttles, but expanding the internal mux to accommodate this being shared between all designs is not currently feasible (while also juggling all the other requirements and safeguards). Not to say that it WON'T happen in the future, though :) For now most people have been doing small amounts of memory using just DFFs, or they have been implementing external memory access via SPI/QPI.

[@dmaynor]

This is awesome. I am signing up next week.

[@fooglestuff]

I'm excited for you, @dmaynor! I hope to cross paths with you on the Tiny Tapeout Discord sometime, and look forward to seeing what you make.

[@davemorphling7432]

I can't find the pdf file shown at 10:05, there's datasheet pdf in tinytapeout-02 repo, but it's missing some info, and github search never works, where's the latest datasheet?

[@fooglestuff]

All of those design datasheet pages I've shown are screenshots from designs found in the main list on this page: tinytapeout.com/runs/tt02/#all-projects -- They are indexed by design ID number. The datasheet PDF is (I think) exactly the same info from all of those individual pages. Many designs are lacking details. Feel free to contact the individual designers (i.e. use the "GitHub repository" links) to tell them you're interested in their design, and encourage them to do a documentation update ;)

[@yoppindia]

I want to understand how switch between different designs happen based on input.

[@СергейСмирнов-ф9к5л]

it's probably just a giant multiplexer selecting outputs from the specific design. So all designs work all the time but only output from the selected design is shown. It could also be that they switch off the clock for designs that are not selected to save power.

[@fooglestuff]

In TT03 & below, all designs connect in series as a scan chain... giant shift register, effectively. "Selecting" a design means sampling only the section of the scan chain that is relevant to that design's position in the chain (which logic in the scan chain handles by monitoring the 9 'Select project' DIP switches). This design explains the slow clock speeds: 20MHz core clock gets divided by all the IO bits of all designs. TT04+ is a big change to make it a giant multiplexer (as pointed out by @user-vd8oy1wh4r), meaning any given design can run at much higher frequencies (30MHz+ expected) and with more IO (inc. some bidir). TT06+ also has power gating to turn off all but the selected design.

[@GraeDay]

Great video. Instant subscription!

[@fooglestuff]

Great to have you on board, @GraeDay! Thanks for your positive feedback :)

[@matthewvenn]

Great video Anton!

[@fooglestuff]

Thank you Matt!

[@oxycada9272]

What is the price of one slot in the chip and the board?

[@pieterboots8566]

What is the maximum clock speed of these chips?

[@fooglestuff]

TT03 and below, the max input clock is ~28MHz, but the huge scan chain linking all designs causes that to be divided by 8000. TT04+ allows a clock of at least 25MHz *directly* into any design, and maybe closer to 33MHz. Interesting is the fact that any individual design could implement its own clock multiplier or ring oscillator and go much faster… 200MHz might be possible. IO bandwidth is limited to ~25MHz too, though.

[@amenia8849]

I am happy to see a opensource chip here. But, what can I do with it, if I cannot change the programs, I just don't get it. I got it now, forget my question.

[@СергейСмирнов-ф9к5л]

You can't change the programs cuz they are manufactured in silicon, that's the whole point. Well, he says there are some designs of FPGA's there, so, technically you can program that chip )))

[@daisywong-ke1kz]

Wonderful work! We'd love to offer you some boards if you need them in the upcoming content. (PCBWay Daisy) :)

[@fooglestuff]

Thank you for the offer Daisy

[@daisywong-ke1kz]

@@fooglestuff NP man, just let us know once you have any needs from us. :p

[@zyxwvutsrqponmlkh]

So can you actually buy these chips. Like I thought there were only like 1 per person who made a design.

[@fooglestuff]

You're mostly right... currently someone who does a submission can purchase only one chip+board kit, because the shuttle itself supplies 100 chips (unless extra shuttle slots are purchased, which makes it a bit of a scaling challenge). There are exceptions to this: someone who purchases enough tiles (I think 4+, say for a larger design or multiple designs) MIGHT (in some TT runs) be eligible to purchase a second kit. Also, if there happens to be surplus from a TT run, that surplus may be offered for sale at a later date. Matt Venn is hoping to find a way to stretch this further in future.

[@zyxwvutsrqponmlkh]

@@fooglestuff So, a normal run costs $10,000 right? But these are $300x100 = $30,000. I know there is overhead producing the demo boards and what not but is there room to lower the price? Also, it seems like the die area on your runs are only half full each time. I suspect this is to lower the interval between runs but it seems wasteful, why not just make the blocks bigger if this is constantly the case. I mean it's still really cool and $300 for prototype silicon is a fabulous price but it would be nice if there were a smoother ramp to small scale production. Quite interested to see how some analog designs turn out. Analog neuro nets on silicon could be really nifty.

[@y_x2]

I don't understand why an ASIC instead of a FPGA.

[@quantumsmith371]

Fun

[@y_x2]

@@quantumsmith371 Nobody is using an ASIC in small qty unless they have very deep pocket.

[@quantumsmith371]

​@@y_x2 Efabless offers 100 QFN packaged parts for $9750. If you went with cheaper packaging you could get about a 1000 parts for that price. Also the more people that do ASICs the cheaper it will get. Most of the cost is in the mask, and mask cost is dominated by raw materials and depreciation if they used cheaper materials or had more customers they could cut that price a lot.

[@greenaum]

@@y_x2 Like the man said, it's entirely for fun! Imagine designing your own silicon, and getting a chip with your circuit actually inside it! Of course, there are a few compromises, but I don't know if any of the designs are supposed to be particularly practical, it's all just for fun. This is the first time members of the public have been able to design their own silicon without needing a ton of money, by having lots of people club together in return for so-many transistors each.

[@fooglestuff]

At this stage it's mostly about learning a new way to design chips that is based on a fully open source workflow (including PDK or Process Development Kit) -- this is quite a different approach to how it has ever been. The other reason is that as of TT06 (now open, closing in about 4 weeks) this method also supports analog and mixed-signal designs, which you won't find on an FPGA. For many contributors though, it is probably as much about FUN (as others have said) as it is about gaining valuable experience in this new way of working that is trying to attract more people to the field.

[@wiwingmargahayu6831]

zamzam water

[@zyxwvutsrqponmlkh]

Eyes too blue.

[@fooglestuff]

Oh yeah, that... it's probably the Spice. Actually it's more a combination of my colour grading being slightly off the mark, and a reflection of a blue monitor screen in my eyes. I'll try to tone it down in future ;)

[@danielburke5097]

Jeez. Some people will complain about anything, Anton. Keep doing what you are doing...🙂

[@fooglestuff]

@@danielburke5097 Thanks Daniel! :)