Tutorial On CMOS VLSI Design of Full Adder | Day On My Plate

[@simran_jain]

I liked the way u explained in easy manner. Kindly upload video of cmos implementation of 1-ripple carry adder 2-carry look ahead adder 3-multiplier 4-barrel shifter And please take care that whole paper is visible. Thank you.

[@DayOnMyPlate]

Sure Simran... coming soon...

[@ravich1549]

Only half paper is visible..

[@DayOnMyPlate]

We are really sorry. We will try to improve it from the next time onwards.

[@tahseenahemad7612]

very helpful sir .. you should also make video on following 1:carry by pass adder 2:linear carry select adder 3:squareroot carry-select adder 4:Array multplixer

[@alokendrapal8179]

Videos r vry helpful 2 me...but in this video full page isn't coming in camera..so plzz be careful of it.otherwise it is great to understand easily.

[@UtpalBhattacharjee]

Cout= Cin(A xor B)+ AB But you have given (A+B) which is wrong

[@asifmuhammed75]

correct me if I'm wrong. shouldn't there be equal number of transistors in pull up and pull down netwrk?

[@ExploreElectronics]

good one

[@deepikachinni25]

where is the step2??complementing the output??

[@vijaysurya5769]

super

[@muhammadasyrafothman1732]

Can you explain more, why does inverter is neeeded in Cout and Sum?

[@devendersinghbohra40]

As the CMOS circuit gives the inverted output so we need to invert it again to get the required output.

[@mounicahasini7709]

half paper is visible sir

[@saidharnesh4261]

paper is not properly visible .....,

[@bourbadjolloff3998]

i'm very happy to find your tutorial. Greetings from Hamburg/Germany

[@urmilapathivada2046]

Sir, good explanation. But I don't understand one thing that while deriving the output expression for sum by using a,b,CIN,cout' as inputs,, you have to take the value each input for logic one output. But you just took the logic one inputs only . Whyyy? I hope I am clear. Sir please do respond

[@DayOnMyPlate]

You can reach me at [e-mail]

[@swetapreeti6243]

keep the paper straight !!!!!

[@froopi2]

Half of it isn't even visible

[@subhrajitmoitra1792]

what r u doing ! only half paper is visible , please do something

[@AyushKumar-se3jk]

Bhai sahi se camera rakho

[@DayOnMyPlate]

Ok. Next time we will surely do that. Thanks for your suggestion.

[@chaitrytrivedi3833]

the best tutorial I've come across ! thank you so much !

[@ExploreElectronics]

kzbin.info/aero/PLu7-Sp50sShcF5r4l-FMYxnjlQOsVbN6U

[@sudheerchakrawarti2636]

Love it Brother.. Liked the way you explained.

[@niveditadey5969]

how the expression for cout be so?the minterms for carry of a full adder are 3,5,6 and 7. the expression would be AB+Cin(A XOR B). please explain a bit detail for that expression.

[@toddblackmon]

Note that (A XOR B) + AB = A!B + !AB + AB = A+B

[@aparajithans5331]

@@toddblackmon where did Cin go

[@toddblackmon]

It was only a hint for the Cin = 1 case. The idea was to expand it by breaking the cases up where Cin = 0 vs Cin = 1. The Cin = 0 case is pretty easy to understand and see. With no carry in, you only carry out when both A and B are set. The Cin = 1 case reduces to AB + (A XOR B), which looks complicated and doesn't seem to match intuition. I was showing that AB + (A XOR B) is actually the same as A+B, matching our intuition of how Cout should work when Cin = 1.

[@locallyringedspace3190]

if you know what a truth table is and sop don't watch this video bc that's all you get

[@hsienchipeng8346]

my neck......

[@bharathgowdajm1290]

Bottom of the page is not visible sir

[@nehashahid6850]

the 3 inputs for carry side should be A,B,Cin ...then y you have taken only 2 inputs at a time.we should take 3 inputs no....????

[@DayOnMyPlate]

neha shahid 2 half adders make 1 full adder circuits. So if you study the block diagram then you can understand that you have to design a half adder 1st with 2 inputs. The output of this 1st HA is taken fresh input for 2nd half adder.

[@amankesharwani9504]

half content is visible

[@HarshSharma-fm3gq]

keep going never come back

[@achu7096]

nice tutorial

[@sumedhsonawane1501]

Bhai paper sidha karke toh sikhata

[@tanaybhaskar3334]

ccc

[@vinayakakarthik4259]

Can u plz send me the layout design or Euler's graph for CMOS full adder mirror circuit

[@santoshsahu880]

nice explanation

[@utsavnath2974]

make videos where the full paper is visible..or don't make it.

[@ritamdutta8098]

The changes will be done at the earliest..

[@bymistakeengineer6727]

The pull up pull down diagram was not visible....

[@mahadihassananik8777]

Make video for stick diagram for layout design.

[@T0R0RIKI]

8:25 excuse me, but how did you find the expression for SUM ? why you didnt account for every term (also negated ones), and write instead only those which are 1 ? which rule did you follow ?

[@DayOnMyPlate]

Since it is sum of product (SOP), therefore max terms (1) to be taken. Similarly, for POS min terms (0) need to be taken.

[@surajchaurasia4336]

Khud ko padha rha h Bhai CMOS Dekh he nhe rha

[@khalidsaifullah1321]

how is Cout is an input of Sout??

[@waferlayout]

I like this so much❤

[@mahadihassananik8777]

love it man .

[@sanjaytomar4148]

Tatti kr di apne to

[@shilpikumari5141]

you u not take compliment Cout ?

[@sherrygupta2513]

cout is output of second half adder.why it is treated as input??? we hv A B and cin as input

[@toddblackmon]

It allows you to reduce the logic a bit if you can use the previously needed cout as an input..

[@DayOnMyPlate]

that is how a full adder operates Sherry.

[@nilaykumar2834]

wtf adjust your camera

[@DayOnMyPlate]

Thank you for your interest in our videos. We are really happy to see your eagerness to see the video. We will surely improve the position and camera from the next time onwards.

[@poojarisubbasreekanthyadav457]

paper is visible half only

[@DayOnMyPlate]

Sorry. Next time we will rectify it.

[@pushpalatha4028]

Sir plz apload full paper once

[@DayOnMyPlate]

Ok. You can reach me at [e-mail]