Tutorial: RISC-V Vector Extension Demystified - 2020 RISC-V Summit

[@naveenchander5349]

Amazing! Probably the only tutorial so far that explains RISC-V Vector Extension in so much detail.

[@MichaelMaitland-yi1gq]

Thank you! Explanations and examples made the vector extension digestible, compared to reading the spec directly.

[@Bonkers123]

Thank you for your insightful video. Is the power point slides available somewhere?

[@santoshkandagave9184]

Are tools/ IDE are free for users to download and start prototyping few RISC-V ISA based intrinsic examples? for NX27V architecture

[@oajugade8917]

Could we get the pdf used in the tutorial?? That would be great!

[@gayathrigp812]

How come the programmer knows that 512 is the maximum VLEN this architecture supports?

[@masonhsieh5583]

I believe you'll need to check the spec. The concept of RVV that Thang brought out here can be applied to other size of VPU. At 35:00, Thang mentioned that the VPU he designed for Andes product has the maximum vlen of 512b.

[@louiscyfear878]

Single instruction Single Data.