COA | Pipeline Hazards & Data Hazard Classifications: RAW, WAW, WAR | Lec 43 | GATE CSE 2021/22 Exam

[@anubhavrai5427]

classs start from 7:58

[@PENJENDRUVARUN-uy2ov]

00:04 Understanding pipeline hazards and data hazard classifications 02:41 Platform features and benefits for online learning 07:59 Pipeline hazards and data hazard classifications 10:59 Pipeline hazards and data hazard classifications 17:07 Compiler generates instructions for CPU 19:38 Explanation of Pipeline Hazards & Data Hazard Classifications 25:08 Understanding pipeline hazards & data hazard classifications 27:36 Pipeline hazards: RAW, WAW, WAR classifications 32:50 Data Hazard Classifications 35:13 Pipeline Hazards & Data Hazard Classifications 40:20 Data hazard classifications 42:51 Pipeline Hazards & Data Hazard Classifications 48:11 Understanding data dependencies and hazards in pipeline operations 51:01 Understanding data dependencies in software 56:22 Pipeline hazards and data hazard classifications 58:42 Pipeline hazards and data hazard classifications 1:04:30 Pipeline hazards and data hazard classifications 1:07:11 Pipeline hazards and data hazard classifications 1:12:16 Understanding branch prediction hardware in CPUs 1:14:45 Prediction of Program Behavior 1:19:46 Subscription benefits and offerings

[@kavithapriyacj4868]

Excellent example for delayed load 🙏👏👏👏👏👏😘😘...vah vah vah...kiya badh sir aapko unique info about a topic

[@codeb3nder862]

That example at 22:00 was excellent! cant forget that

[@ayushs7766]

42:10 beautiful singing !!

[@AS-we3zt]

Very very help full for me .thank you sir for coa complete play list ..🙏🙏

[@akshunair3367]

Great Explanation!

[@sonamsrivastava3074]

Amazing explanation sir ji 🤗👍👍

[@namandhanotia1188]

More than the concepts, I enjoy your songs, stories, jumpado XD..

[@dipakraut6058]

Everything Understood🙌

[@explorerofinternet3426]

42:02 Way better than Tony kakkar's whole career

[@jamespottex5197]

Yaha pe bhi tony... Padhai pe dhyan warna puri jindagi tony tony karta reh jayega yt cmnt section mein

[@explorerofinternet3426]

to tu kya har jagah muh marra h... ek kaam kr tu muh maarne me hi dhyan de purri zindagi yt k cmnt section mai ...kyuki padhai to trese hogi nahi.

[@swastikrana2670]

lol🤣

[@MohitSingh-jb9tb]

amazing lecture , sir..🙏

[@karamsahoo6852]

Amazing video lectures!

[@anisha2444]

Coa seems easier with this guy! ❤️

[@RajGupta-rs6ho]

outstanding content

[@mkalyan2698]

For the code below LD R2 , 0 (R1) LD R3, 4 (R1) ADD R4, R2, R3 SW R4, 12 (R1) LD R5, 8 (R1) ADD R6, R5, R3 SW R6, 16 (R1) Consider each instruction takes 5 clock cycles in an unpipelined architecture and the Pipelined architecture has five stages (IF, ID, EX, MEM, WB) and each stage takes one clock cycle time. (a) Number of clock cycles taken for the code to run in an unpipelined computer is (A) 35 (B) 30 (C) 7 (D) None of the above (b) Dependences that exist are (A) Data and Output (B) Data and Antidependence (C) Only Data (D) None of the above (c) Number of clock cycles taken for the code to run in a pipelined computer with no data forwarding or other compiler techniques to handle data hazards is (A) 11 (B) 13 (C) 17 (D) 23 (d) Number of clock cycles taken for the code to run in a pipelined computer with data forwarding (A) 11 (B) 13 (C) 17 (D) 23 (e) Number of clock cycles taken for the code to run in a pipelined computer when data forwarding and other compiler solutions are applied (A) 9 (B) 11 (C) 13 (D) 17 pls explain sir

[@ayushranjan4470]

Can anyone clear me at 32:15 we are locking the hardware for cycle 4 and 5 (starting from 1 suppose) still we are getting 2 stall cycle so delay is already there so how we are handling delay as stall cycles are already present. Thanks!

[@rishabhgupta9846]

these 2 stalls are for reading data after it is written (Hardware interlock is used when data dependency is present)

[@garrysacademy2122]

Great explanation🥰

[@Aditya-qi2wq]

in which video can i get computer aruthematic, broths algo

[@sandeepsinghgaur2643]

Thanku very much sir

[@OlzVeeru]

7:50

[@darshantechful]

Guys for point 51:25 i found GATE 2005 question .check it out now .

[@ChandanKumar-eh6hp]

I like ur singing sir

[@acko9262]

❤️❤️❤️

[@Lucasroblox-c9x]

In Store instructions r4

[@rishabhgupta9846]

but for load and store ,operand forwarding cannot save stall cycles.Then how are you saying this?

[@nandiniagarwal2646]

🔥🔥🔥

[@sairamkumarkommana1095]

You have not explained data hazard classification RAW,WAR.. Could you please explain it sir

[@adireddy4710]

He did..in the next lecture..44th lecture

[@criticalcommunist5]

44:16 🤣🤣🤣

[@suniljadaun5814]

Sir , what if we don't show our project in viva.. Just explain the project without laptop. sir Laptop nahi laaye..

[@studified596]

💯

[@nishantshukla9493]

Jay hind 🇮🇳

[@Adityasharma-oe8zp]

Haan aise hota tha jab me meri gf ke peeche baitthta tha😂😂😂

[@ganpati2859]

gf, nhi crush bol

[@chessmaniac2136]

Samjh mai aya kya magaj mai aya kya😂

[@_AMIT-ji4gy]