Verilog Code for 2 to 4 Decoder in Modelsim with TestBench | Verilog Tutorial

[@andreavenegas5134]

in a quaternary to binary decoder, how can negative input be implemented in verilog?

[@wikimedia9137]

Can we design verilog decoder by if else statement for bigger decoders

[@sumairaziz9219]

sure, we can.

[@berke4456]

which language is this

[@ChinmaySSinha]

hindi

[@berke4456]

@@ChinmaySSinha thx