Verilog HDL (18EC56) | Module 2 | Lexical Conventions | VTU

[@sailaxmianumula4452]

Very Good explanation sir....Thanks for ur efforts

[@manojpgpmhalli8846]

Thanks sir,ur teaching is awesome 🔥

[@silentcrusader1752]

Great teaching sir 🥺 thanks a lott

[@Udaykumar-bn6eh]

Hi sir.. can i get slides of this notes..

[@vinaykumarhn6845]

Thanks sir

[@appuayyappavlogs5742]

Nice sir