virtual sequence & virtual sequencer w.r.p.t system Verilog UVM.

[@kirtikansal6946]

kudos to the energy that you put in explaining the toughest topic, relating the codes and the diagrams, making the learners more enthusiastic to grasp more.. appreciable efforts.

[@MunsifMAhmad]

Thanks 😊

[@easytunesparks1317]

Informative... Thanks for adding the video...

[@ganeshpatil7199]

Next level explanation... Thank you so much...The explanation is exactly what I was looking for (industry specific)👏🙌😊

[@MunsifMAhmad]

Small correction @6:19 .. Virtual sequencer is a component class in the UVM base class hierarchy, hence it's default constructor has 2 arguments.. @8:58 -> difference between object and component classes.

[@bestenglishlearning5049]

So good in explanation. Good luck Sir.

[@mayankyadav2720]

Very good explanation sir , keep on covering topics sir. Very helpful for us. Keep the good work up ! ❤️

[@AbijithP-y1f]

great job

[@j_______patil2920]

Tqs for explanation 😃😊

[@ichus0098]

What is the use of `uvm_do_on macro and 'uvm_declare_p_sequencer() in UVM virtual sequence ?

[@MunsifMAhmad]

`uvm_do_on This is the same as `uvm_do except that it also sets the parent sequence to the sequence in which the macro is invoked, and it sets the sequencer to the specified SEQR argument. Reference:- verificationacademy.com/verification-methodology-reference/uvm/docs_1.1a/html/files/macros/uvm_sequence_defines-svh.html#:~:text=%60uvm_do_on,-%60uvm_do_on(SEQ_OR_ITEM%2C&text=This%20is%20the%20same%20as%20%60uvm_do%20except%20that%20it%20also,to%20the%20specified%20SEQR%20argument. This macro is used to declare a variable p_sequencer whose type is specified by SEQUENCER. Reference:- verificationacademy.com/verification-methodology-reference/uvm/docs_1.1a/html/files/macros/uvm_sequence_defines-svh.html#%60uvm_declare_p_sequencer

[@Lucky-ks5hz]

Sir Who will write virtual seq and virtual seqr. Testcase writer or tb developer.!

[@MunsifMAhmad]

Generally TB developers..

[@Lucky-ks5hz]

@@MunsifMAhmad tq sir

[@shubhampandey7275]

But here also, in case of multiple agents with seqr, testcase writter gets dependent on testbench writter to know the number of such agents with seqr... Then how is this clearing their dependency??

[@UVLS]

Instead of knowing the entire hierarchy to the agent sequencer , the testcase developer will just get details of virtual sequencer from the testbench developer . which helps testcase developer to develop complex scenarios .

[@rasagnasaranga1405]

Sir explain all the uvm and also have any material please share

[@MunsifMAhmad]

Yes i will try, U can use verification guide, verification academy and UVM Cook Book as a reference..

[@bhadrappavadageri1818]

@@MunsifMAhmad please explain all UVM concepts

[@MunsifMAhmad]

@@bhadrappavadageri1818 will try if possible..

[@tnaveenlatha]

Hi, Can you please explain with two agents..

[@MunsifMAhmad]

Will upload a video soon:)

[@MunsifMAhmad]

You will find two agents in implementation video:)

[@writetorohit]

Is it mandatory to pass parameters to sequence, sequencer,driver classes ?

[@MunsifMAhmad]

Yes.. u can understand it better if look at the handshaking mechanisms between driver and sequence, where sequencer work as a mediator..