VLSI ASIC Design flow

In this video a high level description of VLSI ASIC design flow is discussed.
Entire VLSI design cycle is divided into RTL design, RTL verification, Synthesis and Physical Design.
Watch the video for more information
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[@olajuwonadebayo6674]

This is one of the best explanations I’ve seen on design flow. It’s a must much for every EE/CE student interested in chip design. Thanks for such a wonderful video.

[@jairamgouda]

Thanks a lot for the support 😊

[@VishalYadavYouthMotivator]

Amazing sir crystal clear concept for Asic flow 😍😍Best content till watched .

[@jairamgouda]

Thank you

[@bhavanadhaker3597]

Sir your explanation is so good.👍👍 I found this video after watching 9-10 another senseless videos

[@sangeshs944]

very informative

[@VishalYadavYouthMotivator]

Love the contents very much 😍😍

[@mrsukki8158]

Nice

[@bhanukrishnaraghava8151]

Sir please Do a session on UNIFIED POWER FORMAT

[@jairamgouda]

Will try my best to make a video on UPF. Thanks a lot for your support

[@yerragollanareshkumar9561]

Once said how this asic design flow using in practical ,and its applicatons ,generations

[@mrsukki8158]

Bro linux bagge ondu videos madu

[@jairamgouda]

Sure bro 😁 thanks a lot for your suggestion ☺️

[@adorablegeorgieee9948]

Hiii How is design specification step documented?

[@PuspoAktar-y6e]

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